TQM8xx: use the CFI flash driver on all TQM8xx boards

[karo-tx-uboot.git] / include / configs / TQM860M.h

diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 481e3d0d53250759d6625c36fc00e34cc6e23b6e..8601de17225768b094578c6f7f49c75180e57935 100644 (file)
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -69,8 +69,14 @@
        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
        "rootpath=/opt/eldk/ppc_8xx\0"                                  \
        "bootfile=/tftpboot/TQM860M/uImage\0"                           \
-       "kernel_addr=40080000\0"                                        \
-       "ramdisk_addr=40180000\0"                                       \
+       "fdt_addr=400C0000\0"                                           \
+       "kernel_addr=40100000\0"                                        \
+       "ramdisk_addr=40280000\0"                                       \
+       "load=tftp 200000 ${u-boot}\0"                                  \
+       "update=protect off 40000000 +${filesize};"                     \
+               "erase 40000000 +${filesize};"                          \
+               "cp.b 200000 40000000 ${filesize};"                     \
+               "protect on 40000000 +${filesize}\0"                    \
        ""
 #define CONFIG_BOOTCOMMAND     "run flash_self"
 
@@ -171,7 +177,7 @@
 #define CFG_FLASH_BASE         0x40000000
 #define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
-#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define        CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc()  */
 
 /*
  * For booting Linux, the board info and command line data
@@ -183,21 +189,26 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
-
-#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
-#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI          1       /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER   1       /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE     1
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip */
 
 #define        CFG_ENV_IS_IN_FLASH     1
 #define        CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 #define        CFG_ENV_SIZE            0x08000 /* Total Size of Environment Sector     */
-#define        CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
+#define        CFG_ENV_SECT_SIZE       0x40000 /* Total Size of Environment Sector     */
 
 /* Address and size of Redundant Environment Sector    */
 #define CFG_ENV_OFFSET_REDUND  (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
 
+#define        CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
+
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
@@ -360,7 +371,7 @@
  */
 #define SDRAM_BASE2_PRELIM     0x00000000      /* SDRAM bank #0        */
 #define SDRAM_BASE3_PRELIM     0x20000000      /* SDRAM bank #1        */
-#define        SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
+#define        SDRAM_MAX_SIZE          0x08000000      /* max 128 MB per bank  */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)     */
 #define CFG_OR_TIMING_SDRAM    0x00000A00
@@ -436,7 +447,10 @@
 #define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
                         MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
                         MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
+                        MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
+                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 
 /*
  * Internal Definitions