sunxi: non-FEL SPL boot support for sun7i

[karo-tx-uboot.git] / include / configs / ZPC1900.h

diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 9cda3f9bdf438ccd737321c96a1bf5685ccca221..d76a14072857bb1818f04e7b99c228846bfe2ab8 100644 (file)
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -5,30 +5,16 @@
  * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
  * This port was developed and tested on Revision C board.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU      */
 #define CONFIG_ZPC1900         1       /* ...on Zephyr ZPC.1900 board */
+
+#define        CONFIG_SYS_TEXT_BASE    0xFE000000
+
 #define CPU_ID_STR             "MPC8265"
 #define CONFIG_CPM2            1       /* Has a CPM2 */
 
@@ -73,8 +59,8 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Full duplex
  */
-# define CONFIG_SYS_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 # define CONFIG_SYS_CPMFCR_RAMTYPE     0
 # define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 
@@ -86,6 +72,10 @@
  * GPIO pins used for bit-banged MII communications
  */
 #define MDIO_PORT              2       /* Port C */
+#define MDIO_DECLARE           volatile ioport_t *iop = ioport_addr ( \
+                                       (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE            MDIO_DECLARE
+
 #define MDIO_ACTIVE            (iop->pdir |=  0x00400000)
 #define MDIO_TRISTATE          (iop->pdir &= ~0x00400000)
 #define MDIO_READ              ((iop->pdat &  0x00400000) != 0)
@@ -147,9 +137,7 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_SYS_LONGHELP                    /* undef to save memory     */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size  */
 #else
@@ -164,8 +152,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR           0x400000        /* default load address */
 
-#define CONFIG_SYS_HZ                  1000    /* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
@@ -188,9 +174,8 @@
 #define BCSR_PCI_MODE          0x01
 
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x4000  /* Size of used area in DPRAM   */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
@@ -208,10 +193,8 @@
 #define CONFIG_SYS_HRCW_SLAVE6         0
 #define CONFIG_SYS_HRCW_SLAVE7         0
 
-#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM          0x02    /* Software reboot                  */
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #endif