ppc4xx: Remove 4xx NAND booting support

[karo-tx-uboot.git] / include / configs / bamboo.h

diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 97da1e9078ac4ab67a67b9a471ece0cdb8cbc740..6ba4aaf8cb78c584cb1f3187bf52417ebdd8276f 100644 (file)
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -86,12 +86,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1   /* use FLASH for environment vars       */
-#else
-#define CONFIG_ENV_IS_IN_NAND  1       /* use NAND for environment vars        */
-#define CONFIG_ENV_IS_EMBEDDED 1       /* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -120,61 +115,6 @@
 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.        sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST   0x00800000      /* Copy SPL here                */
-#define CONFIG_SYS_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
-#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE      512             /* NAND chip page size          */
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
-#define CONFIG_SYS_NAND_PAGE_COUNT     32              /* NAND chip page count         */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE   1               /* Fourth addr used (>32MB)     */
-
-#define CONFIG_SYS_NAND_ECCSIZE        256
-#define CONFIG_SYS_NAND_ECCBYTES       3
-#define CONFIG_SYS_NAND_OOBSIZE        16
-#define CONFIG_SYS_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET              (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -182,15 +122,7 @@
 #define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
-
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS             1
-#else
-#define CONFIG_SYS_NAND_CS             0               /* NAND chip connected to CSx   */
-/* Memory Bank 0 (NAND-FLASH) initialization                                   */
-#define CONFIG_SYS_EBC_PB0AP           0x018003c0
-#define CONFIG_SYS_EBC_PB0CR           (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -226,7 +158,6 @@
        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
-       CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
        "kernel_addr=fff00000\0"                                        \
        "ramdisk_addr=fff10000\0"                                       \
        ""