Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / include / configs / bf537-pnav.h

diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 8daebc884672aba73a5cc9f5cf6cbb50f1b046da..ba74a695f88b03d8ab6c06481e8702e452de97b7 100644 (file)
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -52,7 +52,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL        0x7BB033B0
 #define CONFIG_EBIU_AMBCTL1_VAL        0xFFC27BB0
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)
 
 
@@ -63,12 +63,11 @@
 #define ADI_CMDS_NETWORK       1
 #define CONFIG_BFIN_MAC
 #define CONFIG_RMII
-#define CONFIG_NET_MULTI       1
 #endif
 #define CONFIG_HOSTNAME                bf537-pnav
 /* Uncomment next line to use fixed MAC address */
 /* #define CONFIG_ETHADDR      02:80:ad:24:21:18 */
-
+#define CONFIG_LIB_RAND
 
 /*
  * Flash Settings
@@ -112,13 +111,10 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-       arch/blackfin/cpu/traps.o               (.text .text.*); \
-       arch/blackfin/cpu/interrupt.o   (.text .text.*); \
-       arch/blackfin/cpu/serial.o              (.text .text.*); \
-       common/dlmalloc.o               (.text .text.*); \
-       lib/crc32.o             (.text .text.*); \
+       arch/blackfin/lib/built-in.o (.text*); \
+       arch/blackfin/cpu/built-in.o (.text*); \
        . = DEFINED(env_offset) ? env_offset : .; \
-       common/env_embedded.o           (.text .text.*);
+       common/env_embedded.o (.text*);
 #endif
 
 
@@ -132,7 +128,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF12
 #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@ -141,13 +136,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-       do { \
-               bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
-               bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
-               bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
-       } while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 
 
 /*