*/
#define CONFIG_SYS_I2C_SOFT
#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Run core 1 from L1 SRAM start address when init uboot on core 0