#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
/* Cogent Modular Architecture options */
#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
#define CONFIG_CMD_KGDB
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Low Level Cogent settings
- * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
+ * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
* (second 2 for CMA120 only)
*/
-#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
+#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
#include <configs/cogent_common.h>
#ifdef CONFIG_CONS_NONE
-#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
+#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
#endif
-#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
+#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
#define CONFIG_SHOW_ACTIVITY
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
* defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
*/
-#define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
/* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_IMMR 0xF0000000
+#define CONFIG_SYS_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE CMA_MB_RAM_BASE
+#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
-#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
+#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
#else
-#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
+#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
#endif
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
+#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
-#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
+#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
#else
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
*
* HID1 has only read-only information - nothing to set.
*/
-#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2 0
+#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
*-----------------------------------------------------------------------
* turn on Checkstop Reset Enable
*/
-#define CFG_RMR RMR_CSRE
+#define CONFIG_SYS_RMR RMR_CSRE
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
-#define CFG_BCR BCR_EBM
+#define CONFIG_SYS_BCR BCR_EBM
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
-#define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
+#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 4-35
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
-#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
-#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
-#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
* Ensure DFBRG is Divide by 16
*/
-#define CFG_SCCR (SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
-#define CFG_RCCR 0
+#define CONFIG_SYS_RCCR 0
#if defined(CONFIG_CMA282)
* (the *_SIZE vars must be a power of 2)
*/
-#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
-#define CFG_CMA_CS0_SIZE (1 << 20)
+#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
+#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
#if 0
-#define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
-#define CFG_CMA_CS2_SIZE (16 << 20)
+#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
+#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
#endif
/*
* CS0 maps the EPROM on the cpu module
- * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
+ * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
*
* Note: We must have already transferred control to the final location
* of the EPROM before these are used, because when BR0/OR0 are set, the
* mirror of the eprom at any other addresses will disappear.
*/
-/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
-#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
-/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
-#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
+/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
+#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
+#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
/*
*/
#if 0
-/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
-#define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
-/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
-#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
+/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
+#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
+#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blobdiff