*
* Configuration settings for the DevKit8000 board.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
+#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SYS_TEXT_BASE 0x80008000
+#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#define CONFIG_NAND
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+#include <configs/ti_omap3_common.h>
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/* Size of malloc() pool */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
+#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
- /* initial data */
/* Hardware drivers */
-
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR 1
-
/* DM9000 */
-#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x2c000000
#define CONFIG_DM9000_NO_SROM 1
#undef CONFIG_DM9000_DEBUG
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* MMC */
-#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
-#define CONFIG_DOS_PARTITION 1
+/* SPI */
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
/* I2C */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#undef CONFIG_SYS_I2C_OMAP24XX
+#define CONFIG_SYS_I2C_OMAP34XX
/* TWL4030 */
-#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/* Board NAND Info */
-#define CONFIG_SYS_NO_FLASH /* no NOR flash */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:" \
"512k(x-loader)," \
"4m(kernel)," \
"-(fs)"
-#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* partition */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP /* DHCP support */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_GPIO
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BOOTZ
+#undef CONFIG_SUPPORT_RAW_INITRD
+#undef CONFIG_FAT_WRITE
+#undef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_FS_GENERIC
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
#undef CONFIG_BOOTP_VENDOREX
/* Environment information */
-#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
-
-#define CONFIG_BOOTDELAY 3
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
+ "console=ttyO2,115200n8\0" \
+ "mmcdev=0\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"run commonargs; " \
"setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 " \
+ "rootwait " \
"${kernelopts}\0" \
"nandargs=" \
"run commonargs; " \
"${kernelopts} " \
"dnsip1=${dnsip} " \
"dnsip2=${dnsip2}\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"dhcp ${loadaddr}; " \
"run netargs; " \
"bootm ${loadaddr}\0" \
- "autoboot=if mmc init 0; then " \
+ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
#define CONFIG_BOOTCOMMAND "run autoboot"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
-
/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
0x01000000) /* 16MB */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
-#endif
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
/* NAND and environment organization */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET boot_flash_off
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+
+/* SRAM config */
+#define CONFIG_SYS_SRAM_START 0x40200000
+#define CONFIG_SYS_SRAM_SIZE 0x10000
+
+/* Defines for SPL */
+#undef CONFIG_SPL_MTD_SUPPORT
+
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
+
+/* SPL OS boot options */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
+#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+ 0x400000)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+
+#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
+
+#undef CONFIG_SYS_SPL_ARGS_ADDR
+#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#endif /* __CONFIG_H */
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