Merge branch 'master' of git://git.denx.de/u-boot-spi

[karo-tx-uboot.git] / include / configs / io.h

diff --git a/include/configs/io.h b/include/configs/io.h
index 33743e61ac0951b7e655d28daafcffa8dc463f7d..9da6cc685592b95d5593c04cbe54b300d2451fe8 100644 (file)
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -2,14 +2,13 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #define CONFIG_405EP           1       /* this is a PPC405 CPU */
-#define CONFIG_4xx             1       /*  member of PPC4xx family */
 #define CONFIG_IO              1       /*  on a Io board */
 
 #define        CONFIG_SYS_TEXT_BASE    0xFFFC0000
@@ -18,7 +17,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME                io
-#define CONFIG_IDENT_STRING    " io 0.05"
+#define CONFIG_IDENT_STRING    " io 0.06"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -123,7 +122,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION    1       /* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO    /* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST    1       /* no warn upon unknown flash */
@@ -200,9 +198,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE       128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-       (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+       (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -230,6 +227,11 @@
 
 #define CONFIG_SYS_FPGA_COUNT          1
 
+#define CONFIG_SYS_FPGA_PTR \
+       { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE          0x7f200000
 #define CONFIG_SYS_EBC_PB3AP           0xa2015480