ARM: remove broken "kb9202" board

[karo-tx-uboot.git] / include / configs / m501sk.h

diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index f09214dce9c37d5b76c57f4a2653a5e541000755..68f0415a37b839a79e2d14dbeb39b3126e57c3cd 100644 (file)
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -27,6 +27,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MAIN_CLOCK       179712000
@@ -34,6 +36,7 @@
 #define AT91C_MASTER_CLOCK     59904000
 #define AT91_SLOW_CLOCK        32768 /* slow clock */
 
+#define CONFIG_AT91RM9200      1       /* It's an Atmel AT91RM9200 SoC */
 #define CONFIG_AT91RM9200DK    1 /* on an AT91RM9200DK Board    */
 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
 #define CONFIG_CMDLINE_TAG     1 /* enable passing of ATAGs    */
@@ -41,12 +44,39 @@
 #define CONFIG_INITRD_TAG              1
 
 #define CONFIG_MENUPROMPT              "."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL   0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL    0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* Bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE                        115200
 
@@ -77,6 +107,7 @@
 #define CONFIG_CMC_PU2
 
 /* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_AT91RM9200_USART
 #define CONFIG_DBGU
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -121,18 +152,13 @@
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_PROMPT_HUSH_PS2         ">>"
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     0 /* Max number of NAND devices */
-#define SECTORSIZE                          512
-
-#define ADDR_COLUMN            1
-#define ADDR_PAGE              2
-#define ADDR_COLUMN_PAGE       3
 
 #define CONFIG_NR_DRAM_BANKS   1
 #define PHYS_SDRAM             0x20000000
@@ -142,7 +168,13 @@
 /* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
 #define CONFIG_SYS_MEMTEST_END 0x00100000
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI               1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC         1
+#define CONFIG_SYS_RX_ETH_BUFFER       8
+#else
+#define CONFIG_DRIVER_ETHER            1
+#endif
 #define CONFIG_NET_RETRY_COUNT 20
 #define CONFIG_AT91C_USE_RMII