DEBUG: Fix debug macros

[karo-tx-uboot.git] / include / configs / pdnb3.h

diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index f8aac1aba3ddd453984864444961777cba6667a8..56bb4641fca84a9d846214508f77f68f80c94bb1 100644 (file)
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -40,7 +40,6 @@
  * Ethernet
  */
 #define CONFIG_IXP4XX_NPE      1       /* include IXP4xx NPE support   */
-#define CONFIG_NET_MULTI       1
 #define        CONFIG_PHY_ADDR         16      /* NPE0 PHY address             */
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR       18      /* NPE1 PHY address             */
@@ -50,8 +49,6 @@
 /*
  * Misc configuration options
  */
-#define CONFIG_USE_IRQ          1      /* we need IRQ stuff for timer  */
-
 #define CONFIG_BOOTCOUNT_LIMIT         /* support for bootcount limit  */
 #define CONFIG_SYS_BOOTCOUNT_ADDR      0x60003000 /* inside qmrg sram          */
 
@@ -63,11 +60,11 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          (1 << 20)
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_IXP_SERIAL
 #define CONFIG_BAUDRATE         115200
 #define CONFIG_SYS_IXP425_CONSOLE      IXP425_UART1   /* we use UART1 for console */
 
@@ -116,7 +113,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
-#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#define CONFIG_IXP425_TIMER_CLK                66666666
 #define CONFIG_SYS_HZ                  1000            /* decrementer freq: 1 ms ticks */
                                                /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +185,7 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE          0x50000000
 #define CONFIG_SYS_FLASH_BASE          0x50000000
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
@@ -264,7 +262,7 @@
  * NAND-FLASH stuff
  */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x51000000      /* NAND FLASH Base Address      */
+#define CONFIG_SYS_NAND_BASE           0x51000000      /* NAND FLASH Base Address */
 #endif
 
 /*
@@ -345,4 +343,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR        \
+       (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */