cosmetic: s/BOARD_LATE_INIT/CONFIG_BOARD_LATE_INIT

[karo-tx-uboot.git] / include / configs / pxa255_idp.h

diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index fa53cf445376c273e5b2367d02c75c9020d69067..620d270893e4338f94757d2347f2662e88102b8c 100644 (file)
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -42,7 +42,7 @@
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #undef CONFIG_SKIP_LOWLEVEL_INIT                       /* define for developing */
-#undef CONFIG_SKIP_RELOCATE_UBOOT                      /* define for developing */
+#define        CONFIG_SYS_TEXT_BASE    0x0
 
 /*
  * define the following to enable debug blinks.  A debug blink function
@@ -64,15 +64,17 @@
 
 #define CONFIG_MMC             1
 #define CONFIG_DOS_PARTITION   1
-#define BOARD_LATE_INIT                1
+#define CONFIG_BOARD_LATE_INIT
 
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 
 /*
  * PXA250 IDP memory map information
@@ -84,7 +86,7 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE   (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
 #define CONFIG_SMC_USE_32_BIT  1
 /* #define CONFIG_SMC_USE_IOFUNCS */
@@ -97,6 +99,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART         1       /* we use FFUART on LUBBOCK */
 
 /* allow to overwrite serial and ethaddr */
@@ -119,7 +122,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_DHCP
 
@@ -237,8 +239,6 @@
 #define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 
-#undef CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
-
 #define CONFIG_SYS_LOAD_ADDR           0xa0800000      /* default load address */
 
 #define CONFIG_SYS_HZ                  1000
@@ -249,7 +249,11 @@
                                                /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
 #define CONFIG_SYS_MMC_BASE            0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -265,7 +269,7 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS   4          /* we have 1 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS   1          /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1           0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE      0x04000000 /* 64 MB */
 #define PHYS_SDRAM_2           0xa4000000 /* SDRAM Bank #2 */
@@ -286,6 +290,9 @@
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define        CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
@@ -308,6 +315,9 @@
 
 #define CONFIG_SYS_PSSR_VAL            0x20
 
+#define        CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
+#define        CONFIG_SYS_CKEN                 0x0
+
 /*
  * Memory settings
  */
@@ -317,6 +327,8 @@
 #define CONFIG_SYS_MDCNFG_VAL          0x090009C9
 #define CONFIG_SYS_MDREFR_VAL          0x0085C017
 #define CONFIG_SYS_MDMRS_VAL           0x00220022
+#define        CONFIG_SYS_FLYCNFG_VAL          0x00000000
+#define        CONFIG_SYS_SXCNFG_VAL           0x00000000
 
 /*
  * PCMCIA and CF Interfaces