/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_SERVERIP 10.10.69.49
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME QUANTUM
-#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
+#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
#define CONFIG_BOOTARGS "root=/dev/ram rw"
/*
* Select the more full-featured memory test (Barr embedded systems)
*/
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
#endif
/* NVRAM and RTC */
-#define CFG_NVRAM_BASE_ADDR 0xFA000000
-#define CFG_NVRAM_SIZE 2048
+#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
+#define CONFIG_SYS_NVRAM_SIZE 2048
/*
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x00040000 /* memtest works on */
-#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_IMMR 0xFA200000
+#define CONFIG_SYS_IMMR 0xFA200000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFF000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xFF000000
#if 1
- #define CFG_FLASH_CFI_DRIVER
+ #define CONFIG_FLASH_CFI_DRIVER
#else
- #undef CFG_FLASH_CFI_DRIVER
+ #undef CONFIG_FLASH_CFI_DRIVER
#endif
-#ifdef CFG_FLASH_CFI_DRIVER
- #define CFG_FLASH_CFI 1
- #undef CFG_FLASH_USE_BUFFER_WRITE
- #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#ifdef CONFIG_FLASH_CFI_DRIVER
+ #define CONFIG_SYS_FLASH_CFI 1
+ #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#endif
-/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
+/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */
#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
-#define CFG_MONITOR_BASE 0xFFF00000
-/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
+/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/
-#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
-#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/* FPGA */
#define CONFIG_MISC_INIT_R
-#define CFG_FPGA_SPARTAN2
-#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_SPARTAN2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
/*-----------------------------------------------------------------------
* Reset address
*/
-#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
-#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#define CFG_SIUMCR (SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
-#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
-/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*/
#define SCCR_MASK SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
+#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
-#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR (0xEC000000)
-#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET 0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
-/*#define CFG_DER 0x2002000F*/
-#define CFG_DER 0
+/*#define CONFIG_SYS_DER 0x2002000F*/
+#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
*/
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
-#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
/*
* BR1 and OR1 (SDRAM)
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CFG_OR_TIMING_SDRAM 0x00000E00
+#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
-#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
-#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
-#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */
-#define CFG_OR3_PRELIM 0xFFFF8910
+#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */
+#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
-#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
-#define CFG_OR4_PRELIM 0xFFFE0970
+#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
-#define CFG_MAMR_PTA 20
+#define CONFIG_SYS_MAMR_PTA 20
/*
* Refresh clock Prescalar
*/
-#define CFG_MPTPR MPTPR_PTP_DIV2
+#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
/*
* MAMR settings for SDRAM
*/
/* 9 column SDRAM */
-#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* BCSRx
*
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