/*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+/* M41T11 Serial Access Timekeeper(R) SRAM */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "system"
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFF800000
-/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
-#define CFG_MONITOR_BASE 0xFFF00000
-/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x00740000 /* Offset of Environment Sector */
+#define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000)
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
* BR0 and OR0 (FLASH)
*/
-#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
-#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
+#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
+#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
-#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
+#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
+/* IMMR: 0xFA200000 IMMR base address - see above */
+#define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */
+
+#define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */
#define CFG_OR3_PRELIM 0xFFFF8910
-#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
+#define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
#define CFG_OR4_PRELIM 0xFFFE0970
/*
*
*/
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
+#define BCSR0 (CFG_BCSR_BASE + 0)
+#define BCSR1 (CFG_BCSR_BASE + 1)
+#define BCSR2 (CFG_BCSR_BASE + 2)
+#define BCSR3 (CFG_BCSR_BASE + 3)
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
+#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
projects / karo-tx-uboot.git / blobdiff