#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+/* PCI */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+
+#define CONFIG_PCI_MEM_BUS 0x80000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x71000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_PCI_CFG_BUS 0x70000000
+#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
+#define CONFIG_PCI_CFG_SIZE 0x01000000
+
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP | \
- 0)
-
-/* CFG_CMD_MII | \ */
-/* CFG_CMD_PCI | \ */
-/* CFG_CMD_USB | \ */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
/*
* Default Environment
#define CONFIG_HOSTNAME sorcery
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
/*
* I2C configuration
/*
* Flexbus Chipselect configuration
- * Beware: Some CS# seem to be mandatory (if these CS# are not set,
- * board can hang-up in unpredictable place).
+ * Beware: Some CS# seem to be mandatory (if these CS# are not set,
+ * board can hang-up in unpredictable place).
* Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
*/
/* Flash */
#define CFG_CS0_BASE 0xf800
#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */
-
-/* Workaround of hang-up after setting ctrl register for flash
- After reset this register has value 0x003ffd80, which differs
- from suggested only by the number of wait states.
-#define CFG_CS0_CTRL 0x003f1580
-*/
+#define CFG_CS0_CTRL 0x001019c0
/* NVM */
-#define CFG_CS1_BASE 0xf100
-#define CFG_CS1_MASK 0x00080000 /* 512K */
-#define CFG_CS1_CTRL 0x003ffd40 /* 8bit port size? */
+#define CFG_CS1_BASE 0xf7e8
+#define CFG_CS1_MASK 0x00040000 /* 256K */
+#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */
/* Atlas2 + Gemini */
-/* This CS# is mandatory? */
-#define CFG_CS2_BASE 0xf10A
-#define CFG_CS2_MASK 0x00020000 /* 2x64K*/
-#define CFG_CS2_CTRL 0x003ffd00 /* 32bit port size? */
+#define CFG_CS2_BASE 0xf7e7
+#define CFG_CS2_MASK 0x00010000 /* 64K*/
+#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */
/* CAN Controller */
-/* This CS# is mandatory? */
-#define CFG_CS3_BASE 0xf10C
+#define CFG_CS3_BASE 0xf7e6
#define CFG_CS3_MASK 0x00010000 /* 64K */
-#define CFG_CS3_CTRL 0x003ffd40 /* 8Bit port size */
+#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */
/* Foreign interface */
-#define CFG_CS4_BASE 0xF10D
+#define CFG_CS4_BASE 0xf7e5
#define CFG_CS4_MASK 0x00010000 /* 64K */
-#define CFG_CS4_CTRL 0x003ffd80 /* 16bit port size */
+#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */
-/* CPLD? */
-/* This CS# is mandatory? */
-#define CFG_CS5_BASE 0xF108
-#define CFG_CS5_MASK 0x00010000
-#define CFG_CS5_CTRL 0x003ffd80 /* 16bit port size */
+/* CPLD */
+#define CFG_CS5_BASE 0xf7e4
+#define CFG_CS5_MASK 0x00010000 /* 64K */
+#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */
#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
-#define CFG_FLASH_BASE CFG_FLASH0_BASE
+#define CFG_FLASH_BASE (CFG_FLASH0_BASE)
-#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks (actually 4? (at least 2)) */
-#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip (actually 256) */
-
-
-#define PHYS_AMD_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
CFG_FLASH_BASE+0x04000000 } /* two banks */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (CFG_FLASH0_BASE)
-#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
-#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000)
+#define CFG_ENV_SIZE 0x4000 /* 16K */
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM configuration (for SPD) */
#define CFG_SDRAM_TOTAL_BANKS 1
-#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
+#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
#define CFG_SDRAM_SPD_SIZE 0x100
-#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
+#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
+
+/* SDRAM drive strength register (for SSTL_2 class II)*/
+#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
+ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
+ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
/*
* Ethernet configuration
#define CONFIG_MPC8220_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_MII 1
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
-#define CFG_HID0_INIT 0
-#define CFG_HID0_FINAL 0
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+
+/*
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+*/
#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blobdiff