Exynos5420: Introduce support for the Peach-Pit board

[karo-tx-uboot.git] / include / configs / tegra20-common.h

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index e464e06173e8bf570e166a0d69b4a9bb13485bcc..21bf9771742424dcf4da509e8550a2964b585b0a 100644 (file)
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -2,32 +2,20 @@
  *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _TEGRA20_COMMON_H_
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
 /*
  * Errata configuration
  */
+#define CONFIG_ARM_ERRATA_716044
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_751472
 
@@ -36,11 +24,6 @@
  */
 #define V_NS16550_CLK          216000000       /* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20                         /* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x00408000      /* def. location for kernel */
 
@@ -61,6 +44,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -78,6 +64,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x10000000\0" \
+       "pxefile_addr_r=0x10100000\0" \
        "kernel_addr_r=0x01000000\0" \
        "fdt_addr_r=0x02000000\0" \
        "ramdisk_addr_r=0x02100000\0"
@@ -87,8 +74,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START    0x00090000
 #define CONFIG_SPL_STACK               0x000ffffc
 
-#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/tegra20/u-boot-spl.lds"
-
 /* Align LCD to 1MB boundary */
 #define CONFIG_LCD_ALIGNMENT   MMU_SECTION_SIZE
 
@@ -110,6 +95,7 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH  10
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS      4