avr32: delete non generic board mimc200

[karo-tx-uboot.git] / include / configs / tegra30-common.h

diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 282caec44b9e09414fe0da2699fa3e6e71945a98..3e8e3c1e5bd9f3d282c8bd383acc358eb3cb9abc 100644 (file)
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -2,46 +2,30 @@
  *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _TEGRA30_COMMON_H_
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
 /*
- * NS16550 Configuration
+ * Errata configuration
  */
-#define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
 
 /*
- * High Level Configuration Options
+ * NS16550 Configuration
  */
-#define CONFIG_TEGRA30                 /* in a NVidia Tegra30 core */
-
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR                0x80408000      /* def. location for kernel */
+#define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR   0x80A00800      /* default */
 #define CONFIG_STACKBASE       0x82800000      /* 40MB */
 
 /*-----------------------------------------------------------------------
@@ -55,6 +39,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -70,9 +57,11 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
+#define CONFIG_LOADADDR 0x81000000
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x90000000\0" \
-       "kernel_addr_r=0x81000000\0" \
+       "pxefile_addr_r=0x90100000\0" \
+       "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
        "fdt_addr_r=0x82000000\0" \
        "ramdisk_addr_r=0x82100000\0"
 
@@ -81,6 +70,9 @@
 #define CONFIG_SYS_SPL_MALLOC_START    0x80090000
 #define CONFIG_SPL_STACK               0x800ffffc
 
-#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/tegra30/u-boot-spl.lds"
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */