* esd vme8349 U-Boot configuration file
* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* reinhard.arlt@esd-electronics.de
#ifndef __CONFIG_H
#define __CONFIG_H
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_CADDY2
+#define VME_CADDY2
+#endif
+
/*
* High Level Configuration Options
*/
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
+#define CONFIG_MISC_INIT_R
+
#define CONFIG_PCI
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define PCI_66M
-#ifdef PCI_66M
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
*/
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_READ_SPD vme8349_read_spd
#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
/*
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 512 /* MB */
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | \
- CSCONFIG_BANK_BIT_3)
-#endif
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x39377322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE 0x07940242
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-/* autocharge,no open page */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
+#define CONFIG_SYS_DDRCDR 0x80080001
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+#ifdef VME_CADDY2
+#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 16bit */ \
+ BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
+#else
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 32bit */ \
+ (2 << BR_PS_SHIFT) | /* 16bit */ \
BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
+#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
+#endif
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200)
+#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e)
+#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
-#undef CONFIG_SYS_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
/*
* Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
+ * LCRR: no DLL bypass, Clock divider is 4
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CONFIG_NET_MULTI
+#ifndef VME_CADDY2
+#endif
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define PCI_IDSEL_NUMBER 0xFIXME
#endif
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
#endif /* CONFIG_PCI */
/*
* TSEC configuration
*/
+#ifdef VME_CADDY2
+#define CONFIG_E1000
+#else
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#endif
#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI
-#endif
-#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_GMII /* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_HOSTNAME VME8349
-#define CONFIG_ROOTPATH /tftpboot/rootfs
-#define CONFIG_BOOTFILE uImage
+#define CONFIG_ROOTPATH "/tftpboot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* boot command will set bootargs */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 9600
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
#define CONFIG_BOOTCOMMAND "run flash_self"
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+#endif
+
#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blobdiff