Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / include / ddr_spd.h

diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 6fdcef0c0af795987f828b757f2c7e2fbe90b2e8..9e74d8729e23c2a56c48424a84a8a76210a66529 100644 (file)
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -184,7 +184,7 @@ typedef struct ddr3_spd_eeprom_s {
        unsigned char module_type;     /*  3 Key Byte / Module Type */
        unsigned char density_banks;   /*  4 SDRAM Density and Banks */
        unsigned char addressing;      /*  5 SDRAM Addressing */
-       unsigned char res_6;           /*  6 Reserved */
+       unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
        unsigned char organization;    /*  7 Module Organization */
        unsigned char bus_width;       /*  8 Module Memory Bus Width */
        unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
@@ -219,7 +219,14 @@ typedef struct ddr3_spd_eeprom_s {
                                             Delay Time*/
        unsigned char opt_features;    /* 30 SDRAM Optional Features */
        unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
-       unsigned char res_32_59[28];   /* 32-59 Reserved, General Section */
+       unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
+       unsigned char device_type;     /* 33 SDRAM device type */
+       int8_t fine_tCK_min;           /* 34 Fine offset for tCKmin */
+       int8_t fine_tAA_min;           /* 35 Fine offset for tAAmin */
+       int8_t fine_tRCD_min;          /* 36 Fine offset for tRCDmin */
+       int8_t fine_tRP_min;           /* 37 Fine offset for tRPmin */
+       int8_t fine_tRC_min;           /* 38 Fine offset for tRCmin */
+       unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 
        /* Module-Specific Section: Bytes 60-116 */
        union {
@@ -243,6 +250,20 @@ typedef struct ddr3_spd_eeprom_s {
                        unsigned char mod_thickness;
                        /* 62 (Registered) Reference Raw Card Used */
                        unsigned char ref_raw_card;
+                       /* 63 DIMM Module Attributes */
+                       unsigned char modu_attr;
+                       /* 64 RDIMM Thermal Heat Spreader Solution */
+                       unsigned char thermal;
+                       /* 65 Register Manufacturer ID Code, Least Significant Byte */
+                       unsigned char reg_id_lo;
+                       /* 66 Register Manufacturer ID Code, Most Significant Byte */
+                       unsigned char reg_id_hi;
+                       /* 67 Register Revision Number */
+                       unsigned char reg_rev;
+                       /* 68 Register Type */
+                       unsigned char reg_type;
+                       /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
+                       unsigned char rcw[8];
                } registered;
                unsigned char uc[57]; /* 60-116 Module-Specific Section */
        } mod_section;
@@ -273,6 +294,7 @@ extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
+extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 
 /*
  * Byte 2 Fundamental Memory Types.
@@ -289,4 +311,31 @@ extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE  (0x0A)
 #define SPD_MEMTYPE_DDR3       (0x0B)
 
+/* DIMM Type for DDR2 SPD (according to v1.3) */
+#define DDR2_SPD_DIMMTYPE_UNDEFINED    (0x00)
+#define DDR2_SPD_DIMMTYPE_RDIMM                (0x01)
+#define DDR2_SPD_DIMMTYPE_UDIMM                (0x02)
+#define DDR2_SPD_DIMMTYPE_SO_DIMM      (0x04)
+#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
+#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
+#define DDR2_SPD_DIMMTYPE_MICRO_DIMM   (0x08)
+#define DDR2_SPD_DIMMTYPE_MINI_RDIMM   (0x10)
+#define DDR2_SPD_DIMMTYPE_MINI_UDIMM   (0x20)
+
+/* Byte 3 Key Byte / Module Type for DDR3 SPD */
+#define DDR3_SPD_MODULETYPE_MASK       (0x0f)
+#define DDR3_SPD_MODULETYPE_RDIMM      (0x01)
+#define DDR3_SPD_MODULETYPE_UDIMM      (0x02)
+#define DDR3_SPD_MODULETYPE_SO_DIMM    (0x03)
+#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
+#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
+#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
+#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07)
+#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM       (0x08)
+#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM       (0x09)
+#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM       (0x0A)
+#define DDR3_SPD_MODULETYPE_LRDIMM     (0x0B)
+#define DDR3_SPD_MODULETYPE_16B_SO_DIMM        (0x0C)
+#define DDR3_SPD_MODULETYPE_32B_SO_DIMM        (0x0D)
+
 #endif /* _DDR_SPD_H_ */