x86: gpio: add pinctrl support from the device tree

[karo-tx-uboot.git] / include / fdtdec.h

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 659047097a1001ca5f007e55b16343ddc214ca78..4fb8a2a1ba52faf11913812955d69966ee1aecdc 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -130,6 +130,9 @@ enum fdt_compat_id {
        COMPAT_NVIDIA_TEGRA20_KBC,      /* Tegra20 Keyboard */
        COMPAT_NVIDIA_TEGRA20_NAND,     /* Tegra2 NAND controller */
        COMPAT_NVIDIA_TEGRA20_PWM,      /* Tegra 2 PWM controller */
+       COMPAT_NVIDIA_TEGRA124_DC,      /* Tegra 124 Display controller */
+       COMPAT_NVIDIA_TEGRA124_SOR,     /* Tegra 124 Serial Output Resource */
+       COMPAT_NVIDIA_TEGRA124_PMC,     /* Tegra 124 power mgmt controller */
        COMPAT_NVIDIA_TEGRA20_DC,       /* Tegra 2 Display controller */
        COMPAT_NVIDIA_TEGRA124_SDMMC,   /* Tegra124 SDMMC controller */
        COMPAT_NVIDIA_TEGRA30_SDMMC,    /* Tegra30 SDMMC controller */
@@ -145,8 +148,6 @@ enum fdt_compat_id {
        COMPAT_SAMSUNG_EXYNOS5_SOUND,   /* Exynos Sound */
        COMPAT_WOLFSON_WM8994_CODEC,    /* Wolfson WM8994 Sound Codec */
        COMPAT_GOOGLE_CROS_EC_KEYB,     /* Google CROS_EC Keyboard */
-       COMPAT_SAMSUNG_EXYNOS_EHCI,     /* Exynos EHCI controller */
-       COMPAT_SAMSUNG_EXYNOS5_XHCI,    /* Exynos5 XHCI controller */
        COMPAT_SAMSUNG_EXYNOS_USB_PHY,  /* Exynos phy controller for usb2.0 */
        COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
        COMPAT_SAMSUNG_EXYNOS_TMU,      /* Exynos TMU */
@@ -175,8 +176,10 @@ enum fdt_compat_id {
        COMPAT_AMS_AS3722,              /* AMS AS3722 PMIC */
        COMPAT_INTEL_ICH_SPI,           /* Intel ICH7/9 SPI controller */
        COMPAT_INTEL_QRK_MRC,           /* Intel Quark MRC */
+       COMPAT_INTEL_X86_PINCTRL,       /* Intel ICH7/9 pin control */
        COMPAT_SOCIONEXT_XHCI,          /* Socionext UniPhier xHCI */
        COMPAT_INTEL_PCH,               /* Intel PCH */
+       COMPAT_INTEL_IRQ_ROUTER,        /* Intel Interrupt Router */
 
        COMPAT_COUNT,
 };
@@ -804,6 +807,83 @@ int fdtdec_decode_memory_region(const void *blob, int node,
                                const char *mem_type, const char *suffix,
                                fdt_addr_t *basep, fdt_size_t *sizep);
 
+/* Display timings from linux include/video/display_timing.h */
+enum display_flags {
+       DISPLAY_FLAGS_HSYNC_LOW         = 1 << 0,
+       DISPLAY_FLAGS_HSYNC_HIGH        = 1 << 1,
+       DISPLAY_FLAGS_VSYNC_LOW         = 1 << 2,
+       DISPLAY_FLAGS_VSYNC_HIGH        = 1 << 3,
+
+       /* data enable flag */
+       DISPLAY_FLAGS_DE_LOW            = 1 << 4,
+       DISPLAY_FLAGS_DE_HIGH           = 1 << 5,
+       /* drive data on pos. edge */
+       DISPLAY_FLAGS_PIXDATA_POSEDGE   = 1 << 6,
+       /* drive data on neg. edge */
+       DISPLAY_FLAGS_PIXDATA_NEGEDGE   = 1 << 7,
+       DISPLAY_FLAGS_INTERLACED        = 1 << 8,
+       DISPLAY_FLAGS_DOUBLESCAN        = 1 << 9,
+       DISPLAY_FLAGS_DOUBLECLK         = 1 << 10,
+};
+
+/*
+ * A single signal can be specified via a range of minimal and maximal values
+ * with a typical value, that lies somewhere inbetween.
+ */
+struct timing_entry {
+       u32 min;
+       u32 typ;
+       u32 max;
+};
+
+/*
+ * Single "mode" entry. This describes one set of signal timings a display can
+ * have in one setting. This struct can later be converted to struct videomode
+ * (see include/video/videomode.h). As each timing_entry can be defined as a
+ * range, one struct display_timing may become multiple struct videomodes.
+ *
+ * Example: hsync active high, vsync active low
+ *
+ *                                 Active Video
+ * Video  ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________
+ *       |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
+ *       |          |   porch  |                    |   porch   |
+ *
+ * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯
+ *
+ * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________
+ */
+struct display_timing {
+       struct timing_entry pixelclock;
+
+       struct timing_entry hactive;            /* hor. active video */
+       struct timing_entry hfront_porch;       /* hor. front porch */
+       struct timing_entry hback_porch;        /* hor. back porch */
+       struct timing_entry hsync_len;          /* hor. sync len */
+
+       struct timing_entry vactive;            /* ver. active video */
+       struct timing_entry vfront_porch;       /* ver. front porch */
+       struct timing_entry vback_porch;        /* ver. back porch */
+       struct timing_entry vsync_len;          /* ver. sync len */
+
+       enum display_flags flags;               /* display flags */
+};
+
+/**
+ * fdtdec_decode_display_timing() - decode display timings
+ *
+ * Decode display timings from the supplied 'display-timings' node.
+ * See doc/device-tree-bindings/video/display-timing.txt for binding
+ * information.
+ *
+ * @param blob         FDT blob
+ * @param node         'display-timing' node containing the timing subnodes
+ * @param index                Index number to read (0=first timing subnode)
+ * @param config       Place to put timings
+ * @return 0 if OK, -FDT_ERR_NOTFOUND if not found
+ */
+int fdtdec_decode_display_timing(const void *blob, int node, int index,
+                                struct display_timing *config);
 /**
  * Set up the device tree ready for use
  */