Merge branch 'karo-tx-uboot' into kc-merge

[karo-tx-uboot.git] / include / fsl_ddr.h

diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index e03f9db5f2e1b10b8ff49ab0180ca11e84ddf10a..3286c95907c2419e3ccdc6cdc05a8245357459a5 100644 (file)
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -9,11 +9,35 @@
 #ifndef FSL_DDR_MAIN_H
 #define FSL_DDR_MAIN_H
 
+#include <fsl_ddrc_version.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 
 #include <common_timing_params.h>
 
+#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+/* All controllers are for main memory */
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      CONFIG_NUM_DDR_CONTROLLERS
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR_LE
+#define ddr_in32(a)    in_le32(a)
+#define ddr_out32(a, v)        out_le32(a, v)
+#define ddr_setbits32(a, v)    setbits_le32(a, v)
+#define ddr_clrbits32(a, v)    clrbits_le32(a, v)
+#define ddr_clrsetbits32(a, clear, set)        clrsetbits_le32(a, clear, set)
+#else
+#define ddr_in32(a)    in_be32(a)
+#define ddr_out32(a, v)        out_be32(a, v)
+#define ddr_setbits32(a, v)    setbits_be32(a, v)
+#define ddr_clrbits32(a, v)    clrbits_be32(a, v)
+#define ddr_clrsetbits32(a, clear, set)        clrsetbits_be32(a, clear, set)
+#endif
+
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
+
+u32 fsl_ddr_get_version(void);
+
 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
  * Bind the main DDR setup driver's generic names
@@ -44,6 +68,13 @@ typedef struct {
        memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
        common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
        fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+       unsigned int first_ctrl;
+       unsigned int num_ctrls;
+       unsigned long long mem_base;
+       unsigned int dimm_slots_per_ctrl;
+       int (*board_need_mem_reset)(void);
+       void (*board_mem_reset)(void);
+       void (*board_mem_de_reset)(void);
 } fsl_ddr_info_t;
 
 /* Compute steps */
@@ -59,7 +90,6 @@ typedef struct {
 unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                                       unsigned int size_only);
-
 const char *step_to_string(unsigned int step);
 
 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
@@ -89,10 +119,11 @@ void fsl_ddr_set_lawbar(
 int fsl_ddr_interactive_env_var_exists(void);
 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-                          unsigned int ctrl_num);
+                    unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+void board_add_ram_info(int use_default);
 
 /* processor specific function */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,