fsl_esdhc: Fix DMA transfer completion waiting loop

[karo-tx-uboot.git] / include / fsl_nfc.h

diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index 279aaa55de055a792e150e658dec5e88a4d14bfd..ff537b49a9cce88e36ee5a78f794edb754e4cde5 100644 (file)
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -24,49 +24,48 @@
 #define __FSL_NFC_H
 
 /*
- * TODO: Use same register defs for nand_spl mxc nand driver
- * and mtd mxc nand driver.
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
  *
- * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in various i.MX devices.
+ * MX31 and MX27 have version 1, which has:
+ *     4 512-byte main buffers and
+ *     4 16-byte spare buffers
+ *     to support up to 2K byte pagesize nand.
+ *     Reading or writing a 2K page requires 4 FDI/FDO cycles.
  *
- * MX31 and MX27 have version 1 which has
- *     4 512 byte main buffers and
- *     4 16 byte spare buffers
- *     to support up to 2K byte pagesize nand.
- *     Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 has version 1.1 which has
- *     8 512 byte main buffers and
- *     8 64 byte spare buffers
- *     to support up to 4K byte pagesize nand.
- *     Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- *      Also some of registers are moved and/or changed meaning as seen below.
+ * MX25 and MX35 have version 2.1, which has:
+ *     8 512-byte main buffers and
+ *     8 64-byte spare buffers
+ *     to support up to 4K byte pagesize nand.
+ *     Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *     Also some of registers are moved and/or changed meaning as seen below.
  */
-#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
 #define MXC_NFC_V1
-#elif defined(CONFIG_MX25)
-#define MXC_NFC_V1_1
+#define is_mxc_nfc_1()         1
+#define is_mxc_nfc_21()                0
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_NFC_V2_1
+#define is_mxc_nfc_1()         0
+#define is_mxc_nfc_21()                1
 #else
-#warning "MXC NFC version not defined"
+#error "MXC NFC implementation not supported"
 #endif
 
 #if defined(MXC_NFC_V1)
 #define NAND_MXC_NR_BUFS               4
 #define NAND_MXC_SPARE_BUF_SIZE                16
 #define NAND_MXC_REG_OFFSET            0xe00
-#define NAND_MXC_2K_MULTI_CYCLE                1
-#elif defined(MXC_NFC_V1_1)
+#define NAND_MXC_2K_MULTI_CYCLE
+#elif defined(MXC_NFC_V2_1)
 #define NAND_MXC_NR_BUFS               8
 #define NAND_MXC_SPARE_BUF_SIZE                64
 #define NAND_MXC_REG_OFFSET            0x1e00
-#else
-#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
 #endif
 
 struct fsl_nfc_regs {
-       u32 main_area[NAND_MXC_NR_BUFS][512/4];
-       u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+       u8 main_area[NAND_MXC_NR_BUFS][0x200];
+       u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
        /*
         * reserved size is offset of nfc registers
         * minus total main and spare sizes
@@ -74,44 +73,43 @@ struct fsl_nfc_regs {
        u8 reserved1[NAND_MXC_REG_OFFSET
                - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
 #if defined(MXC_NFC_V1)
-       u16 bufsiz;
+       u16 buf_size;
        u16 reserved2;
-       u16 buffer_address;
-       u16 flash_add;
+       u16 buf_addr;
+       u16 flash_addr;
        u16 flash_cmd;
-       u16 configuration;
+       u16 config;
        u16 ecc_status_result;
-       u16 ecc_rslt_main_area;
-       u16 ecc_rslt_spare_area;
-       u16 nf_wr_prot;
-       u16 unlock_start_blk_add;
-       u16 unlock_end_blk_add;
-       u16 nand_flash_wr_pr_st;
-       u16 nand_flash_config1;
-       u16 nand_flash_config2;
-#elif defined(MXC_NFC_V1_1)
+       u16 rsltmain_area;
+       u16 rsltspare_area;
+       u16 wrprot;
+       u16 unlockstart_blkaddr;
+       u16 unlockend_blkaddr;
+       u16 nf_wrprst;
+       u16 config1;
+       u16 config2;
+#elif defined(MXC_NFC_V2_1)
        u16 reserved2[2];
-       u16 buffer_address;
-       u16 flash_add;
+       u16 buf_addr;
+       u16 flash_addr;
        u16 flash_cmd;
-       u16 configuration;
-       u16 ecc_status_result;
-       u16 ecc_status_result2;
+       u16 config;
+       u32 ecc_status_result;
        u16 spare_area_size;
-       u16 nf_wr_prot;
+       u16 wrprot;
        u16 reserved3[2];
-       u16 nand_flash_wr_pr_st;
-       u16 nand_flash_config1;
-       u16 nand_flash_config2;
+       u16 nf_wrprst;
+       u16 config1;
+       u16 config2;
        u16 reserved4;
-       u16 unlock_start_blk_add0;
-       u16 unlock_end_blk_add0;
-       u16 unlock_start_blk_add1;
-       u16 unlock_end_blk_add1;
-       u16 unlock_start_blk_add2;
-       u16 unlock_end_blk_add2;
-       u16 unlock_start_blk_add3;
-       u16 unlock_end_blk_add3;
+       u16 unlockstart_blkaddr;
+       u16 unlockend_blkaddr;
+       u16 unlockstart_blkaddr1;
+       u16 unlockend_blkaddr1;
+       u16 unlockstart_blkaddr2;
+       u16 unlockend_blkaddr2;
+       u16 unlockstart_blkaddr3;
+       u16 unlockend_blkaddr3;
 #endif
 };
 
@@ -157,7 +155,7 @@ struct fsl_nfc_regs {
  */
 #define NFC_INT                0x8000
 
-#ifdef MXC_NFC_V1_1
+#ifdef MXC_NFC_V2_1
 #define NFC_4_8N_ECC   (1 << 0)
 #endif
 #define NFC_SP_EN      (1 << 2)
@@ -167,5 +165,6 @@ struct fsl_nfc_regs {
 #define NFC_RST                (1 << 6)
 #define NFC_CE         (1 << 7)
 #define NFC_ONE_CYCLE  (1 << 8)
+#define NFC_FP_INT     (1 << 11)
 
 #endif /* __FSL_NFC_H */