Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

[karo-tx-uboot.git] / include / ppc4xx.h

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index c71da6084405cedde696408679eedab84e134faf..e216663a86de7a4a1864a0af10ad6bfc07f61e82 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,62 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_460SX)
+
+#define PLB_ARBITER_BASE               0x80
+
+#define plb0_revid                     (PLB_ARBITER_BASE + 0x00)
+#define plb0_acr                       (PLB_ARBITER_BASE + 0x01)
+#define plb0_acr_ppm_mask              0xF0000000
+#define plb0_acr_ppm_fixed             0x00000000
+#define plb0_acr_ppm_fair              0xD0000000
+#define plb0_acr_hbu_mask              0x08000000
+#define plb0_acr_hbu_disabled          0x00000000
+#define plb0_acr_hbu_enabled           0x08000000
+#define plb0_acr_rdp_mask              0x06000000
+#define plb0_acr_rdp_disabled          0x00000000
+#define plb0_acr_rdp_2deep             0x02000000
+#define plb0_acr_rdp_3deep             0x04000000
+#define plb0_acr_rdp_4deep             0x06000000
+#define plb0_acr_wrp_mask              0x01000000
+#define plb0_acr_wrp_disabled          0x00000000
+#define plb0_acr_wrp_2deep             0x01000000
+
+#define plb0_besrl                     (PLB_ARBITER_BASE + 0x02)
+#define plb0_besrh                     (PLB_ARBITER_BASE + 0x03)
+#define plb0_bearl                     (PLB_ARBITER_BASE + 0x04)
+#define plb0_bearh                     (PLB_ARBITER_BASE + 0x05)
+#define plb0_ccr                       (PLB_ARBITER_BASE + 0x08)
+
+#define plb1_acr                       (PLB_ARBITER_BASE + 0x09)
+#define plb1_acr_ppm_mask              0xF0000000
+#define plb1_acr_ppm_fixed             0x00000000
+#define plb1_acr_ppm_fair              0xD0000000
+#define plb1_acr_hbu_mask              0x08000000
+#define plb1_acr_hbu_disabled          0x00000000
+#define plb1_acr_hbu_enabled           0x08000000
+#define plb1_acr_rdp_mask              0x06000000
+#define plb1_acr_rdp_disabled          0x00000000
+#define plb1_acr_rdp_2deep             0x02000000
+#define plb1_acr_rdp_3deep             0x04000000
+#define plb1_acr_rdp_4deep             0x06000000
+#define plb1_acr_wrp_mask              0x01000000
+#define plb1_acr_wrp_disabled          0x00000000
+#define plb1_acr_wrp_2deep             0x01000000
+
+#define plb1_besrl                     (PLB_ARBITER_BASE + 0x0A)
+#define plb1_besrh                     (PLB_ARBITER_BASE + 0x0B)
+#define plb1_bearl                     (PLB_ARBITER_BASE + 0x0C)
+#define plb1_bearh                     (PLB_ARBITER_BASE + 0x0D)
+
+#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
+
 #if defined(CONFIG_440)
 /*
  * Enable long long (%ll ...) printf format on 440 PPC's since most of
@@ -147,6 +203,19 @@ typedef struct
        unsigned long pllPlbDiv;
 } PPC4xx_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+       u32 val;
+
+       asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+       return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+       asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __PPC4XX_H__ */