mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes

[karo-tx-uboot.git] / include / zynqpl.h

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 6107cbf3a5a9c98c44951b013adee0cab949e3d8..c81446e9860cb6b5a067fd9c0eec1d47e4ff0327 100644 (file)
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
 extern int zynq_info(Xilinx_desc *desc);
 
 #define XILINX_ZYNQ_7010       0x2
+#define XILINX_ZYNQ_7015       0x1b
 #define XILINX_ZYNQ_7020       0x7
 #define XILINX_ZYNQ_7030       0xc
 #define XILINX_ZYNQ_7045       0x11
@@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc);
 
 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE    16669920/8
+#define XILINX_XC7Z015_SIZE    28085344/8
 #define XILINX_XC7Z020_SIZE    32364512/8
 #define XILINX_XC7Z030_SIZE    47839328/8
 #define XILINX_XC7Z045_SIZE    106571232/8
@@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
 
+#define XILINX_XC7Z015_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+
 #define XILINX_XC7Z020_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }