X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fzynq%2Fcpu.c;h=9af340e75ed052fe4a6701f5c77646d067eb6c60;hp=4367d1afacf3044d81608adc6652aaa118eb7544;hb=d44a5f51288aec60c6bdb4ac939d75c24e5bf9c2;hpb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 4367d1afac..9af340e75e 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
  *
- * SPDX-License-Identifier:	GPL-2.0+ 
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
@@ -10,27 +10,34 @@
 #include <asm/arch/hardware.h>
 
 void lowlevel_init(void)
+{
+}
+
+int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
-	/* remap DDR to zero, FILTERSTART */
-	writel(0, &scu_base->filter_start);
 
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
 	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
 	writel(0x1F, &slcr_base->ocm_cfg);
 	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
 	writel(0x0, &slcr_base->fpga_rst_ctrl);
-	/* TZ_DDR_RAM, Set DDR trust zone non-secure */
-	writel(0xFFFFFFFF, &slcr_base->trust_zone);
 	/* Set urgent bits with register */
 	writel(0x0, &slcr_base->ddr_urgent_sel);
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
+#endif
 
 	zynq_slcr_lock();
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)