X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Ftegra20-common%2Fwarmboot.c;h=5fdc4bbb500700ceaf60c99330ff9e6a7476a032;hp=809ea0133ebaa6871d64db8186282546b6fb29b2;hb=3deb22a4844cbda1a05c60dd29d8926e4dddaa4e;hpb=6e2fbdea1b26d75314d87c380a36b0015bf824cf

diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 809ea0133e..5fdc4bbb50 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -2,51 +2,36 @@
  * (C) Copyright 2010 - 2011
  * NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/fuse.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/gp_padctrl.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
 #endif
 
 /*
  * This is the place in SRAM where the SDRAM parameters are stored. There
  * are 4 blocks, one for each RAM code
  */
-#define SDRAM_PARAMS_BASE	(AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE	(NV_PA_BASE_SRAM + 0x188)
 
 /* TODO: If we later add support for the Misc GP controller, refactor this */
 union xm2cfga_reg {
@@ -138,10 +123,11 @@ int warmboot_save_sdram_params(void)
 {
 	u32 ram_code;
 	struct sdram_params sdram;
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct apb_misc_pp_ctlr *apb_misc =
+				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	struct apb_misc_gp_ctlr *gp =
-			(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+			(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
 	union scratch2_reg scratch2;
 	union scratch4_reg scratch4;
@@ -151,8 +137,8 @@ int warmboot_save_sdram_params(void)
 	union fbio_spare_reg fbio_spare;
 
 	/* get ram code that is used as index to array sdram_params in BCT */
-	ram_code = (readl(&pmt->pmt_strap_opt_a) >>
-			STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+	ram_code = (readl(&apb_misc->strapping_opt_a) >>
+			  STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
 	memcpy(&sdram,
 	       (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
 	       sizeof(sdram));
@@ -205,7 +191,7 @@ static u32 get_major_version(void)
 {
 	u32 major_id;
 	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
 	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
 			HIDREV_MAJORPREV_SHIFT;
@@ -229,7 +215,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
 
 static int ap20_is_odm_production_mode(void)
 {
-	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
 	if (!is_failure_analysis_mode(fuse) &&
 	    is_odm_production_mode_fuse_set(fuse))
@@ -240,7 +226,7 @@ static int ap20_is_odm_production_mode(void)
 
 static int ap20_is_production_mode(void)
 {
-	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
 	if (get_major_version() == 0)
 		return 1;
@@ -257,7 +243,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
 {
 	u32 chip_id;
 	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
 	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
 			HIDREV_CHIPID_SHIFT;
@@ -361,8 +347,8 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length)
 	/* Populate the header. */
 	dst_header->length_insecure = length + sizeof(struct wb_header);
 	dst_header->length_secure = length + sizeof(struct wb_header);
-	dst_header->destination = AP20_WB_RUN_ADDRESS;
-	dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+	dst_header->destination = NV_WB_RUN_ADDRESS;
+	dst_header->entry_point = NV_WB_RUN_ADDRESS;
 	dst_header->code_length = length;
 
 	if (is_encrypted) {