X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx6%2Fcrm_regs.h;h=cee9c434553b834c701780653dd35146e0c19938;hp=76764571a700b9e7d64ef4ebb0b0d5c884a83b26;hb=10919fda8f38907b285a44598f196cca4b52b0c6;hpb=412665b46134f93464c09405e02f08ac9c62526d diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 76764571a7..cee9c43455 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1,25 +1,13 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ +#define CCM_CCOSR 0x020c4060 #define CCM_CCGR0 0x020C4068 #define CCM_CCGR1 0x020C406c #define CCM_CCGR2 0x020C4070 @@ -67,70 +55,29 @@ struct mxc_ccm_reg { u32 CCGR6; /* 0x0080 */ u32 CCGR7; u32 cmeor; - u32 resv[0xfdd]; - u32 analog_pll_sys; /* 0x4000 */ - u32 analog_pll_sys_set; - u32 analog_pll_sys_clr; - u32 analog_pll_sys_tog; - u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ - u32 analog_usb1_pll_480_ctrl_set; - u32 analog_usb1_pll_480_ctrl_clr; - u32 analog_usb1_pll_480_ctrl_tog; - u32 analog_reserved0[4]; - u32 analog_pll_528; /* 0x4030 */ - u32 analog_pll_528_set; - u32 analog_pll_528_clr; - u32 analog_pll_528_tog; - u32 analog_pll_528_ss; /* 0x4040 */ - u32 analog_reserved1[3]; - u32 analog_pll_528_num; /* 0x4050 */ - u32 analog_reserved2[3]; - u32 analog_pll_528_denom; /* 0x4060 */ - u32 analog_reserved3[3]; - u32 analog_pll_audio; /* 0x4070 */ - u32 analog_pll_audio_set; - u32 analog_pll_audio_clr; - u32 analog_pll_audio_tog; - u32 analog_pll_audio_num; /* 0x4080*/ - u32 analog_reserved4[3]; - u32 analog_pll_audio_denom; /* 0x4090 */ - u32 analog_reserved5[3]; - u32 analog_pll_video; /* 0x40a0 */ - u32 analog_pll_video_set; - u32 analog_pll_video_clr; - u32 analog_pll_video_tog; - u32 analog_pll_video_num; /* 0x40b0 */ - u32 analog_reserved6[3]; - u32 analog_pll_vedio_denon; /* 0x40c0 */ - u32 analog_reserved7[7]; - u32 analog_pll_enet; /* 0x40e0 */ - u32 analog_pll_enet_set; - u32 analog_pll_enet_clr; - u32 analog_pll_enet_tog; - u32 analog_pfd_480; /* 0x40f0 */ - u32 analog_pfd_480_set; - u32 analog_pfd_480_clr; - u32 analog_pfd_480_tog; - u32 analog_pfd_528; /* 0x4100 */ - u32 analog_pfd_528_set; - u32 analog_pfd_528_clr; - u32 analog_pfd_528_tog; }; #endif /* Define the bits in register CCR */ #define MXC_CCM_CCR_RBC_EN (1 << 27) -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) +#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 -#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 +/* CCR_WB does not exist on i.MX6SX/UL */ +#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCR_OSCNT_MASK 0x7F +#else #define MXC_CCM_CCR_OSCNT_MASK 0xFF +#endif #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +/* Exists on i.MX6QP */ +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) /* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -151,758 +98,1104 @@ struct mxc_ccm_reg { /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET) /* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) +#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) +/* MMDC_CH0 not exists on i.MX6SX */ +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET) #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET) #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 /* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) +#ifndef CONFIG_SOC_MX6SX +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) +#endif +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) +#endif #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) +/* Exists on i.MX6QP */ +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) /* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 +#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) +/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 +/* CSCMR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 + #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F /* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 +#endif +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 +/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 + +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 /* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) +#ifndef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) +#endif +/* CSCDR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET) +#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 +#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) +#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 + +#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) +#endif +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Define the bits in register CS1CDR */ -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET) +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) +/* QSPI2 on i.MX6SX */ +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET) + +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) + +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 /* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) +#ifndef CONFIG_SOC_MX6SX +#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET) +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28 +#endif +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET) +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 +#else +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 +#endif #define CHSCCDR_CLK_SEL_LDB_DI0 3 #define CHSCCDR_PODF_DIVIDE_BY_3 2 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 /* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 +/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) + +/* All IPU2_DI1 are LCDIF1 on MX6SX */ +#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12 +#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9 +/* All IPU2_DI0 are LCDIF2 on MX6SX */ +#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3 +#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0 /* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) +#endif #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 +#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0) /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) +#endif #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) +#endif +#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 #define MXC_CCM_CLPCR_VSTBY (1 << 8) #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) #define MXC_CCM_CLPCR_SBYOS (1 << 6) #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#ifndef CONFIG_SOC_MX6SX +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) -#define MXC_CCM_CLPCR_LPM_MASK 0x3 +#endif +#define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET) #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CISR_COSC_READY (1 << 6) -#define MXC_CCM_CISR_LRF_PLL 1 +#define MXC_CCM_CISR_LRF_PLL (1 << 0) /* Define the bits in register CIMR */ #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) -#define MXC_CCM_CIMR_MASK_LRF_PLL 1 +#define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Define the bits in register CCOSR */ #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET) #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET) +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET) #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 -#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET) #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 +#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 -#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<