X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx6%2Fimx-regs.h;fp=arch%2Farm%2Finclude%2Fasm%2Farch-mx6%2Fimx-regs.h;h=c0f8f4a72ff0e364a0cb4e5b4f53f638bfcd6fe9;hp=7d721561c9f4d7acedc6b39f789e1d3b991aec1d;hb=ab02058aa07fa8350038076aa9ed86206af5d475;hpb=8c7b57e06e369e0286b6436a8f7a138d59b6dbc6

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7d721561c9..c0f8f4a72f 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -17,21 +17,21 @@
 #define CONFIG_SYS_CACHELINE_SIZE	32
 #endif
 
-#define ROMCP_ARB_BASE_ADDR             0x00000000
-#define ROMCP_ARB_END_ADDR              0x000FFFFF
+#define ROMCP_ARB_BASE_ADDR		0x00000000
+#define ROMCP_ARB_END_ADDR		0x000FFFFF
 
 #ifdef CONFIG_SOC_MX6SL
-#define GPU_2D_ARB_BASE_ADDR            0x02200000
-#define GPU_2D_ARB_END_ADDR             0x02203FFF
-#define OPENVG_ARB_BASE_ADDR            0x02204000
-#define OPENVG_ARB_END_ADDR             0x02207FFF
+#define GPU_2D_ARB_BASE_ADDR		0x02200000
+#define GPU_2D_ARB_END_ADDR		0x02203FFF
+#define OPENVG_ARB_BASE_ADDR		0x02204000
+#define OPENVG_ARB_END_ADDR		0x02207FFF
 #elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define CAAM_ARB_BASE_ADDR              0x00100000
-#define CAAM_ARB_END_ADDR               0x00107FFF
-#define GPU_ARB_BASE_ADDR               0x01800000
-#define GPU_ARB_END_ADDR                0x01803FFF
-#define APBH_DMA_ARB_BASE_ADDR          0x01804000
-#define APBH_DMA_ARB_END_ADDR           0x0180BFFF
+#define CAAM_ARB_BASE_ADDR		0x00100000
+#define CAAM_ARB_END_ADDR		0x00107FFF
+#define GPU_ARB_BASE_ADDR		0x01800000
+#define GPU_ARB_END_ADDR		0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR		0x01804000
+#define APBH_DMA_ARB_END_ADDR		0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR			0x007F8000
 
 #else
@@ -55,7 +55,7 @@
 
 /* GPV - PL301 configuration ports */
 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define GPV2_BASE_ADDR                  0x00D00000
+#define GPV2_BASE_ADDR			0x00D00000
 #else
 #define GPV2_BASE_ADDR			0x00200000
 #endif
@@ -82,28 +82,28 @@
 #define PRIVATE_TIMERS_WD_BASE_ADDR	0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR	0x00A01000
 #define L2_PL310_BASE			0x00A02000
-#define GPV0_BASE_ADDR                  0x00B00000
-#define GPV1_BASE_ADDR                  0x00C00000
+#define GPV0_BASE_ADDR			0x00B00000
+#define GPV1_BASE_ADDR			0x00C00000
 
-#define AIPS1_ARB_BASE_ADDR             0x02000000
-#define AIPS1_ARB_END_ADDR              0x020FFFFF
-#define AIPS2_ARB_BASE_ADDR             0x02100000
-#define AIPS2_ARB_END_ADDR              0x021FFFFF
+#define AIPS1_ARB_BASE_ADDR		0x02000000
+#define AIPS1_ARB_END_ADDR		0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR		0x02100000
+#define AIPS2_ARB_END_ADDR		0x021FFFFF
 /* AIPS3 only on i.MX6SX */
-#define AIPS3_ARB_BASE_ADDR             0x02200000
-#define AIPS3_ARB_END_ADDR              0x022FFFFF
+#define AIPS3_ARB_BASE_ADDR		0x02200000
+#define AIPS3_ARB_END_ADDR		0x022FFFFF
 #ifdef CONFIG_SOC_MX6SX
-#define WEIM_ARB_BASE_ADDR              0x50000000
-#define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI0_AMBA_BASE                0x60000000
-#define QSPI0_AMBA_END                 0x6FFFFFFF
-#define QSPI1_AMBA_BASE                0x70000000
-#define QSPI1_AMBA_END                 0x7FFFFFFF
+#define WEIM_ARB_BASE_ADDR		0x50000000
+#define WEIM_ARB_END_ADDR		0x57FFFFFF
+#define QSPI0_AMBA_BASE			0x60000000
+#define QSPI0_AMBA_END			0x6FFFFFFF
+#define QSPI1_AMBA_BASE			0x70000000
+#define QSPI1_AMBA_END			0x7FFFFFFF
 #elif defined(CONFIG_SOC_MX6UL)
-#define WEIM_ARB_BASE_ADDR              0x50000000
-#define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI0_AMBA_BASE                 0x60000000
-#define QSPI0_AMBA_END                  0x6FFFFFFF
+#define WEIM_ARB_BASE_ADDR		0x50000000
+#define WEIM_ARB_END_ADDR		0x57FFFFFF
+#define QSPI0_AMBA_BASE			0x60000000
+#define QSPI0_AMBA_END			0x6FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR		0x02200000
 #define SATA_ARB_END_ADDR		0x02203FFF
@@ -120,10 +120,10 @@
 #endif
 
 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define MMDC0_ARB_BASE_ADDR             0x80000000
-#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
-#define MMDC1_ARB_BASE_ADDR             0xC0000000
-#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC0_ARB_BASE_ADDR		0x80000000
+#define MMDC0_ARB_END_ADDR		0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR		0xC0000000
+#define MMDC1_ARB_END_ADDR		0xFFFFFFFF
 #else
 #define MMDC0_ARB_BASE_ADDR		0x10000000
 #define MMDC0_ARB_END_ADDR		0x7FFFFFFF
@@ -221,7 +221,7 @@
 
 #define AIPS2_ON_BASE_ADDR		(ATZ2_BASE_ADDR + 0x7C000)
 #define AIPS2_OFF_BASE_ADDR		(ATZ2_BASE_ADDR + 0x80000)
-#define CAAM_BASE_ADDR			(ATZ2_BASE_ADDR)
+#define CAAM_BASE_ADDR			ATZ2_BASE_ADDR
 #define ARM_BASE_ADDR			(ATZ2_BASE_ADDR + 0x40000)
 
 #define CONFIG_SYS_FSL_SEC_ADDR		CAAM_BASE_ADDR
@@ -237,25 +237,25 @@
 #define MLB_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
 
-#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
-#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
-#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
-#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
-#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
-#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
-#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
-#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
-#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+#define USDHC1_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL */
-#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define RNGB_IPS_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x34000)
 #ifdef CONFIG_SOC_MX6UL
-#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define ENET2_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */
-#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define ENET2_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x34000)
 #endif
 /* i.MX6DQ/SDL */
-#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define MMDC_P1_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x34000)
 
 #define WEIM_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x3C000)
@@ -267,68 +267,68 @@
 #else
 #define IP2APB_PERFMON3_BASE_ADDR	(AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
-#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
+#define IP2APB_TZASC1_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x50000)
 #ifdef CONFIG_SOC_MX6UL
-#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI0_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x60000)
 #elif defined(CONFIG_SOC_MX6SX)
-#define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
-#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define SAI1_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SAI2_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
-#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
-#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define IP2APB_TZASC2_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x54000)
+#define MIPI_CSI2_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x64000)
 #endif
-#define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
-#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
-#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
-#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
-#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
-#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
-#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#define MX6UL_WDOG3_BASE_ADDR		(AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE			(AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE			(AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE			(AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE			(AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR			(AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR	(AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR	(AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #ifdef CONFIG_SOC_MX6SX
-#define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
-#define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
-#define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
-#define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
-#define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
-#define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
-#define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
-#define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
-#define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
-#define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
-#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
-#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
-#define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
-#define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
-#define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
-#define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
-#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
-#define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
-#define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
-#define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
-#define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#define GIS_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define LCDIF1_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x20000)
+#define LCDIF2_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x24000)
+#define VADC_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x84000)
+#define ECSPI5_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR			(AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
-#define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define MX6SX_WDOG3_BASE_ADDR		(AIPS3_ARB_BASE_ADDR + 0x88000)
 
 /* only for i.MX6SX/UL */
 #define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
-			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
+				MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
 
-#define CHIP_REV_1_0                 0x10
-#define CHIP_REV_1_2                 0x12
-#define CHIP_REV_1_5                 0x15
-#define CHIP_REV_2_0                 0x20
+#define CHIP_REV_1_0			0x10
+#define CHIP_REV_1_2			0x12
+#define CHIP_REV_1_5			0x15
+#define CHIP_REV_2_0			0x20
 #if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
-#define IRAM_SIZE                    0x00040000
+#define IRAM_SIZE			0x00040000
 #else
 #define IRAM_SIZE			0x00020000
 #endif
@@ -417,33 +417,33 @@ struct src {
 
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
-#define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_GPU_DBG_MASK		(3 << IOMUXC_GPR3_GPU_DBG_OFFSET)
 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
-#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1 << IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
-#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1 << IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
-#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1 << IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
-#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1 << IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
-#define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf << IOMUXC_GPR3_OCRAM_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
-#define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf << IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
-#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1 << IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
-#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1 << IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
-#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1 << IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
-#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1 << IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
-#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1 << IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
-#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1 << IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
-#define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_MASK		(1 << IOMUXC_GPR3_IPU_DIAG_OFFSET)
 
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
@@ -451,16 +451,16 @@ struct src {
 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
 
 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
-#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
-#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
-#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3 << IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
 
 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
-#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3 << IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 
 
 struct iomuxc {
@@ -484,71 +484,71 @@ struct gpc {
 };
 
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
-#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3 << IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
-#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7 << IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
 
 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
-#define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
-#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
-#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0 << IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
 
 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
-#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1 << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW << IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 
 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
-#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
-#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1 << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW << IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 
 #define IOMUXC_GPR2_BITMAP_SPWG	0
 #define IOMUXC_GPR2_BITMAP_JEIDA	1
 
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1 << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG << IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 
 #define IOMUXC_GPR2_DATA_WIDTH_18	0
 #define IOMUXC_GPR2_DATA_WIDTH_24	1
 
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24 << IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
-#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
-#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 
 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
-#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1 << IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
 
 #define IOMUXC_GPR2_MODE_DISABLED	0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
 #define IOMUXC_GPR2_MODE_ENABLED_DI1	3
 
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
-#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1 << IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 
 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
-#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 
 /* ECSPI registers */
 struct cspi_regs {