X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fimx-common%2Fiomux-v3.h;h=0ef633d07b7e27ae1b20e3f622ea2eda75db9d77;hp=ebf54cf187a9dec38df0dc3058ddaed28968f2fe;hb=66b6c2cf7d3ca64d3cf7b3c16b36d0814bb84a8f;hpb=cfd701b5f3eefc98cf699143d34e8a8b737b90a5 diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index ebf54cf187..0ef633d07b 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -5,23 +5,11 @@ * * Copyright (C) 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ +#ifndef __ASM_ARCH_IOMUX_V3_H__ +#define __ASM_ARCH_IOMUX_V3_H__ #include @@ -48,13 +36,13 @@ * * IOMUX/PAD Bit field definitions * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) + * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18) + * SEL_INP: 59..62 (4) + * reserved: 63 (1) */ typedef u64 iomux_v3_cfg_t; @@ -71,11 +59,15 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_SHIFT 36 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) #define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) +#define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID) +#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \ + MUX_PAD_CTRL_SHIFT)) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ sel_input, pad_ctrl) \ @@ -93,76 +85,95 @@ typedef u64 iomux_v3_cfg_t; #define NO_MUX_I 0 #define NO_PAD_I 0 -#define NO_PAD_CTRL (1 << 17) +#define NO_MUX_I 0 +#define NO_PAD_I 0 -#ifdef CONFIG_MX6 +#define NO_PAD_CTRL 0 +#define __PAD_CTRL_VALID (1 << 17) +#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT) -#define PAD_CTL_HYS (1 << 16) +#ifdef CONFIG_ARCH_MX6 -#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) -#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16) -#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13 | PAD_CTL_PKE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) +#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(0 << 6) +#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6) +#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6) -#elif defined(CONFIG_VF610) +#define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3) +#define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3) +#define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3) +#define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3) +#define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3) +#define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3) +#define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3) +#define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3) + +#if defined CONFIG_SOC_MX6SL +#define PAD_CTL_LVE __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_LVE_BIT __MUX_PAD_CTRL(1 << 22) +#endif + +#elif defined(CONFIG_SOC_VF610) #define PAD_MUX_MODE_SHIFT 20 -#define PAD_CTL_SPEED_MED (1 << 12) -#define PAD_CTL_SPEED_HIGH (3 << 12) +#define PAD_CTL_INPUT_DIFFERENTIAL __MUX_PAD_CTRL(1 << 16) + +#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12) +#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12) -#define PAD_CTL_DSE_50ohm (3 << 6) -#define PAD_CTL_DSE_25ohm (6 << 6) -#define PAD_CTL_DSE_20ohm (7 << 6) +#define PAD_CTL_SRE __MUX_PAD_CTRL(1 << 11) +#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 10) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PKE (1 << 3) -#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) +#define PAD_CTL_DSE_150ohm __MUX_PAD_CTRL(1 << 6) +#define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6) +#define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6) +#define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6) -#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE) + +#define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0) +#define PAD_CTL_OBE_ENABLE __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_IBE_ENABLE __MUX_PAD_CTRL(1 << 0) #else -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_INPUT_DDR (1 << 9) -#define PAD_CTL_HYS (1 << 8) +#define PAD_CTL_DVS __MUX_PAD_CTRL(1 << 13) +#define PAD_CTL_INPUT_DDR __MUX_PAD_CTRL(1 << 9) +#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 8) -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 7) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE) -#define PAD_CTL_ODE (1 << 3) +#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 3) -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) +#define PAD_CTL_DSE_LOW __MUX_PAD_CTRL(0 << 1) +#define PAD_CTL_DSE_MED __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_DSE_HIGH __MUX_PAD_CTRL(2 << 1) +#define PAD_CTL_DSE_MAX __MUX_PAD_CTRL(3 << 1) #endif -#define PAD_CTL_SRE_SLOW (0 << 0) -#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW __MUX_PAD_CTRL(0 << 0) +#define PAD_CTL_SRE_FAST __MUX_PAD_CTRL(1 << 0) #define IOMUX_CONFIG_SION 0x10 @@ -176,8 +187,44 @@ typedef u64 iomux_v3_cfg_t; #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) -void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); +void imx_iomux_v3_setup_pad(const iomux_v3_cfg_t const pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction); +void imx_iomux_gpio_get_function(unsigned int gpio, + u32 *gpio_state); +#endif + +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_SOC_MX6QDL) +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD(def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D) +#define IOMUX_PADS(x) MX6Q_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS(x) MX6DL_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif -#endif /* __MACH_IOMUX_V3_H__*/ +#endif /* __ASM_ARCH_IOMUX_V3_H__*/