X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Ffsl_corenet_serdes.c;h=825a29238db2b5fad6e69d8e5cbdb5f612434a12;hp=f5452c07560d5d362a08e59615cdc7676e94b3de;hb=bc5fd908d976cfd898e8cbb591e7220ddc8a684a;hpb=7d6d9ba9d0cb0bb2fefc4ce16c191c1bbad7b656 diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index f5452c0756..825a29238d 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -32,9 +32,19 @@ #include #include "fsl_corenet_serdes.h" -static u32 serdes_prtcl_map; +/* + * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. + * The code is already very complicated as it is, and separating the two + * completely would just make things worse. We try to keep them as separate + * as possible, but for now we require SERDES8 if SERDES_A001 is defined. + */ +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 +#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" +#endif +#endif -#define HWCONFIG_BUFFER_SIZE 128 +static u32 serdes_prtcl_map; #ifdef DEBUG static const char *serdes_prtcl_str[] = { @@ -56,6 +66,7 @@ static const char *serdes_prtcl_str[] = { [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", [XAUI_FM1] = "XAUI_FM1", [XAUI_FM2] = "XAUI_FM2", [AURORA] = "DEBUG", @@ -81,10 +92,17 @@ static const struct { { 17, 163, FSL_SRDS_BANK_2 }, { 18, 164, FSL_SRDS_BANK_2 }, { 19, 165, FSL_SRDS_BANK_2 }, +#ifdef CONFIG_PPC_P4080 { 20, 170, FSL_SRDS_BANK_3 }, { 21, 171, FSL_SRDS_BANK_3 }, { 22, 172, FSL_SRDS_BANK_3 }, { 23, 173, FSL_SRDS_BANK_3 }, +#else + { 20, 166, FSL_SRDS_BANK_3 }, + { 21, 167, FSL_SRDS_BANK_3 }, + { 22, 168, FSL_SRDS_BANK_3 }, + { 23, 169, FSL_SRDS_BANK_3 }, +#endif }; int serdes_get_lane_idx(int lane) @@ -259,9 +277,28 @@ void serdes_reset_rx(enum srds_prtcl device) #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +/* + * Enable a SERDES bank that was disabled via the RCW + * + * We only call this function for SERDES8 and SERDES-A001 in cases we really + * want to enable the bank, whether we actually want to use the lanes or not, + * so make sure at least one lane is enabled. We're only enabling this one + * lane to satisfy errata requirements that the bank be enabled. + * + * We use a local variable instead of srds_lpd_b[] because we want drivers to + * think that the lanes actually are disabled. + */ static void enable_bank(ccsr_gur_t *gur, int bank) { u32 rcw5; + u32 temp_lpd_b = srds_lpd_b[bank]; + + /* + * If we're asked to disable all lanes, just pretend we're doing + * that. + */ + if (temp_lpd_b == 0xF) + temp_lpd_b = 0xE; /* * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in @@ -270,10 +307,10 @@ static void enable_bank(ccsr_gur_t *gur, int bank) rcw5 = in_be32(gur->rcwsr + 5); if (bank == FSL_SRDS_BANK_2) { rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; - rcw5 |= srds_lpd_b[bank] << 26; + rcw5 |= temp_lpd_b << 26; } else if (bank == FSL_SRDS_BANK_3) { rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; - rcw5 |= srds_lpd_b[bank] << 18; + rcw5 |= temp_lpd_b << 18; } else { printf("SERDES: enable_bank: bad bank %d\n", bank + 1); return; @@ -343,8 +380,6 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, */ setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, SRDS_PLLCR1_PLL_BWSEL); - - enable_bank(gur, FSL_SRDS_BANK_3); break; case 0x0f: @@ -379,10 +414,9 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, SRDS_PLLCR0_FRATE_SEL_MASK, SRDS_PLLCR0_FRATE_SEL_6_25); break; - default: - enable_bank(gur, FSL_SRDS_BANK_3); } + enable_bank(gur, FSL_SRDS_BANK_3); } #endif @@ -432,14 +466,44 @@ static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) } #endif +/* + * Wait for the RSTDONE bit to get set, or a one-second timeout. + */ +static void wait_for_rstdone(unsigned int bank) +{ + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned long long end_tick; + u32 rstctl; + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) + printf("SERDES: timeout resetting bank %u\n", bank + 1); +} + + +static void __soc_serdes_init(void) +{ + /* Allow for SoC-specific initialization in _serdes.c */ +}; +void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; +#ifdef CONFIG_PPC_P5040 + serdes_corenet_t *srds2_regs; +#endif int lane, bank, idx; - enum srds_prtcl lane_prtcl; - long long end_tick; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -448,9 +512,10 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - enum srds_prtcl device; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + int need_serdes_a001; /* true == need work-around for SERDES A001 */ #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -460,6 +525,7 @@ void fsl_serdes_init(void) */ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#endif /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -499,6 +565,14 @@ void fsl_serdes_init(void) srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; } + + if ((cfg == 0xf) || (cfg == 0x10)) { + /* + * For SERDES protocols 0xF and 0x10, force bank 3 to be + * disabled, because it is not supported. + */ + srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; + } #endif /* Look for banks with all lanes disabled, and power down the bank. */ @@ -510,6 +584,36 @@ void fsl_serdes_init(void) } } +#ifdef CONFIG_PPC_P5040 + /* + * Lanes on bank 4 on P5040 are commented-out, but for some SERDES + * protocols, these lanes are routed to SATA. We use serdes_prtcl_map + * to decide whether a protocol is supported on a given lane, so SATA + * will be identified as not supported, and therefore not initialized. + * So for protocols which use SATA on bank4, we add SATA support in + * serdes_prtcl_map. + */ + switch (cfg) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; + break; + default: + srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + + /* We don't need bank 4, so power it down */ + setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); + } +#endif + + soc_serdes_init(); + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 /* * Bank two uses the clock from bank three, so if bank two is enabled, @@ -519,15 +623,74 @@ void fsl_serdes_init(void) have_bank[FSL_SRDS_BANK_3] = 1; #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * The work-aroud for erratum SERDES-A001 is needed only if bank two + * is disabled and bank three is enabled. The converse is also true, + * but SERDES8 ensures that bank 3 is always enabled if bank 2 is + * enabled, so there's no point in complicating the code to handle + * that situation. + */ + need_serdes_a001 = + !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; +#endif + + /* Power down the banks we're not interested in */ for (bank = 0; bank < SRDS_MAX_BANK; bank++) { if (!have_bank[bank]) { printf("SERDES: bank %d disabled\n", bank + 1); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * Erratum SERDES-A001 says bank two needs to be powered + * down after bank three is powered up, so don't power + * down bank two here. + */ + if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#else setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_SDPD); +#endif } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A004699 + /* + * To avoid the situation that resulted in the P4080 erratum + * SERDES-8, a given SerDes bank will use the PLLs from the previous + * bank if one of the PLL frequencies is a multiple of the other. For + * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, + * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says + * that, in this situation, lane synchronization is not initiated. So + * when we detect a bank with a "borrowed" PLL, we have to manually + * initiate lane synchronization. + */ + for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { + /* Determine the first lane for this bank */ + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) + if (lanes[lane].bank == bank) + break; + idx = lanes[lane].idx; + + /* + * Check if the PLL for the bank is borrowed. The UOTHL + * bit of the first lane will tell us that. + */ + if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { + /* Manually start lane synchronization */ + setbits_be32(&srds_regs->bank[bank].pllcr0, + SRDS_PLLCR0_PVCOCNT_EN); + } + } +#endif + +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl; + idx = serdes_get_lane_idx(lane); lane_prtcl = serdes_get_prtcl(cfg, lane); @@ -549,6 +712,42 @@ void fsl_serdes_init(void) printf("%s ", serdes_prtcl_str[lane_prtcl]); #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + /* + * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 + * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, + * or AURORA before the device is initialized. + * + * Note that this part of the SERDES-9 work-around is + * redundant if the work-around for A-4580 has already been + * applied via PBI. + */ + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM2_DTSEC1: + case SGMII_FM2_DTSEC2: + case SGMII_FM2_DTSEC3: + case SGMII_FM2_DTSEC4: + case SGMII_FM2_DTSEC5: + case XAUI_FM1: + case XAUI_FM2: + case SRIO1: + case SRIO2: + case AURORA: + out_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_KFR_26 | + SRDS_TTLCR0_FLT_SEL_KPH_28 | + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_FREQOVD_EN); + break; + default: + break; + } +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 switch (lane_prtcl) { case PCIE1: @@ -594,25 +793,17 @@ void fsl_serdes_init(void) serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | FSL_CORENET_DEVDISR2_DTSEC2_4; break; + case SGMII_FM2_DTSEC5: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_5; + break; case XAUI_FM1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + break; case XAUI_FM2: -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - /* - * Set BnTTLCRy0[FLT_SEL] = 000011 and set - * BnTTLCRy0[17] = 1 for each of the SerDes lanes - * selected as XAUI on each bank before XAUI is - * initialized. - */ - clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, - SRDS_TTLCR0_FLT_SEL_MASK, - 0x03000000 | SRDS_TTLCR0_PM_DIS); -#endif - if (lane_prtcl == XAUI_FM1) - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | - FSL_CORENET_DEVDISR2_10GEC1; - else - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | - FSL_CORENET_DEVDISR2_10GEC2; + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; break; case AURORA: break; @@ -622,6 +813,7 @@ void fsl_serdes_init(void) #endif } +#endif #ifdef DEBUG puts("\n"); @@ -632,8 +824,6 @@ void fsl_serdes_init(void) #endif for (idx = 0; idx < SRDS_MAX_BANK; idx++) { - u32 rstctl; - bank = idx; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -664,33 +854,19 @@ void fsl_serdes_init(void) p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, serdes8_devdisr2, cfg); } else if (idx == 2) { - /* Eable bank two now that bank three is enabled. */ + /* Enable bank two now that bank three is enabled. */ enable_bank(gur, FSL_SRDS_BANK_2); } #endif - /* reset banks for errata */ - setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); - - /* wait for reset complete or 1-second timeout */ - end_tick = usec2ticks(1000000) + get_ticks(); - do { - rstctl = in_be32(&srds_regs->bank[bank].rstctl); - if (rstctl & SRDS_RSTCTL_RSTDONE) - break; - } while (end_tick > get_ticks()); - - if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { - printf("SERDES: timeout resetting bank %d\n", - bank + 1); - continue; - } + wait_for_rstdone(bank); } -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - for (device = XAUI_FM1; device <= XAUI_FM2; device++) { - if (is_serdes_configured(device)) - __serdes_reset_rx(srds_regs, cfg, device); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + if (need_serdes_a001) { + /* Bank 3 has been enabled, so now we can disable bank 2 */ + setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, + SRDS_RSTCTL_SDPD); } #endif }