X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8610hpcd%2Fmpc8610hpcd.c;h=2bcd5e6b659f6ee7c4d3ffab0598269bf6c0e678;hp=f67f3e3c56c8dc174917f2975c97bea67e9f3c21;hb=1086c5d6f8541460f0f10e4a302d8aac27e0e6e0;hpb=2e6e1772c0e34871769be4aef79748fe3e47d953 diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index f67f3e3c56..2bcd5e6b65 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -75,14 +76,14 @@ int misc_init_r(void) /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02lx\n",tmp_val); + debug("DVI Encoder Read: 0x%02x\n", tmp_val); tmp_val = 0x10; i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02lx\n",tmp_val); + debug("DVI Encoder Read: 0x%02x\n", tmp_val); return 0; } @@ -93,11 +94,32 @@ int checkboard(void) volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; u8 *pixis_base = (u8 *)PIXIS_BASE; - printf ("Board: MPC8610HPCD, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", + printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); + /* + * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot + * bank and LBMAP=00 is the alternate bank. However, the pixis + * altbank code can only set bits, not clear them, so we treat 00 as + * the normal bank and 11 as the alternate. + */ + switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { + case 0: + puts("vBank: Standard\n"); + break; + case 0x40: + puts("Promjet\n"); + break; + case 0x80: + puts("NAND\n"); + break; + case 0xC0: + puts("vBank: Alternate\n"); + break; + } + mcm->abcr |= 0x00010000; /* 0 */ mcm->hpmr3 = 0x80000008; /* 4c */ mcm->hpmr0 = 0; @@ -123,7 +145,7 @@ initdram(int board_type) setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } @@ -205,98 +227,50 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { #endif -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP -config_table:pci_mpc86xxcts_config_table -#endif -}; +static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel; - int first_free_busno = 0; - int num = 0; - - int pci_agent, pcie_ep, pcie_configured; + struct fsl_pci_info pci_info; + u32 devdisr; + int first_free_busno; + int pci_agent; devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) - >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); -#ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf (" PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf (" PCIE2: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ -#endif + first_free_busno = fsl_pcie_init_board(0); #ifdef CONFIG_PCI1 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf(" PCI connected to PCI slots as %s" \ + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); + printf("PCI: connected to PCI slots as %s" \ " (base address %lx)\n", pci_agent ? "Agent" : "Host", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + pci_info.regs); +#ifndef CONFIG_PCI_PNP + pci1_hose.config_table = pci_mpc86xxcts_config_table; +#endif + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ #endif + + fsl_pcie_init_board(first_free_busno); } #if defined(CONFIG_OF_BOARD_SETUP)