X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=d2d1e8364ffb66236451fb8083f357424373ecba;hp=15340db196a494ab0abf9a036cae419536b0e1d0;hb=0bacb4d60fb1d17a66c032eb13ed8d01599bcc37;hpb=782323c470d7836ff31d1cd7fa978ef161e9cf66 diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index 15340db196..d2d1e8364f 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -1,17 +1,7 @@ /* * Copyright (C) 2012-2015 Lothar Waßmann * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0+ * */ #include @@ -31,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +41,8 @@ #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) +#define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21) +#define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28) #ifdef CONFIG_MX6_TEMPERATURE_MIN #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN @@ -66,30 +59,12 @@ DECLARE_GLOBAL_DATA_PTR; #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) -enum { - MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0) -}; +char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); +#ifdef CONFIG_SECURE_BOOT +char __csf_data[0] __attribute__((section(".__csf_data"))); +#endif static const iomux_v3_cfg_t const tx6qdl_pads[] = { - MX6_PAD_GARBAGE, -#ifdef CONFIG_TX6_NAND_ - /* NAND flash pads */ - MX6_PAD_NANDF_CLE__NAND_CLE, - MX6_PAD_NANDF_ALE__NAND_ALE, - MX6_PAD_NANDF_WP_B__NAND_RESETN, - MX6_PAD_NANDF_RB0__NAND_READY0, - MX6_PAD_NANDF_CS0__NAND_CE0N, - MX6_PAD_SD4_CMD__NAND_RDN, - MX6_PAD_SD4_CLK__NAND_WRN, - MX6_PAD_NANDF_D0__NAND_D0, - MX6_PAD_NANDF_D1__NAND_D1, - MX6_PAD_NANDF_D2__NAND_D2, - MX6_PAD_NANDF_D3__NAND_D3, - MX6_PAD_NANDF_D4__NAND_D4, - MX6_PAD_NANDF_D5__NAND_D5, - MX6_PAD_NANDF_D6__NAND_D6, - MX6_PAD_NANDF_D7__NAND_D7, -#endif /* RESET_OUT */ MX6_PAD_GPIO_17__GPIO7_IO12, @@ -136,20 +111,125 @@ static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { MX6_PAD_ENET_TXD0__ENET_TX_DATA0, }; +#define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) + +static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { + /* internal I2C */ + MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), + MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), +}; + +static const iomux_v3_cfg_t const tx6_i2c_pads[] = { + /* internal I2C */ + MX6_PAD_EIM_D28__I2C1_SDA, + MX6_PAD_EIM_D21__I2C1_SCL, +}; + static const struct gpio const tx6qdl_gpios[] = { + /* These two entries are used to forcefully reinitialize the I2C bus */ + { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", }, + { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", }, + { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", }, { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; -/* - * Functions - */ +static int pmic_addr __data; + +#if defined(CONFIG_SOC_MX6Q) +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c +#define I2C1_SEL_INPUT_VAL 0 +#endif +#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c +#define I2C1_SEL_INPUT_VAL 1 +#endif + +#define GPIO_DR 0 +#define GPIO_DIR 4 +#define GPIO_PSR 8 + +static void tx6_i2c_recover(void) +{ + int i; + int bad = 0; +#define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32)) +#define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32)) + + if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) & + (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) + return; + + debug("Clearing I2C bus\n"); + if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) { + printf("I2C SCL stuck LOW\n"); + bad++; + + writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT, + GPIO3_BASE_ADDR + GPIO_DR); + writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT, + GPIO3_BASE_ADDR + GPIO_DIR); + } + if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) { + printf("I2C SDA stuck LOW\n"); + bad++; + + writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT, + GPIO3_BASE_ADDR + GPIO_DIR); + writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT, + GPIO3_BASE_ADDR + GPIO_DR); + writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT, + GPIO3_BASE_ADDR + GPIO_DIR); + + imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads, + ARRAY_SIZE(tx6_i2c_gpio_pads)); + udelay(10); + + for (i = 0; i < 18; i++) { + u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT; + + debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear"); + writel(reg, GPIO3_BASE_ADDR + GPIO_DR); + udelay(10); + if (reg & SCL_BIT && + readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT) + break; + } + } + if (bad) { + u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR); + + if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) { + printf("I2C bus recovery succeeded\n"); + } else { + printf("I2C bus recovery FAILED: %08x:%08x\n", reg, + SCL_BIT | SDA_BIT); + } + } + debug("Setting up I2C Pads\n"); + imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads, + ARRAY_SIZE(tx6_i2c_pads)); +} + /* placed in section '.data' to prevent overwriting relocation info * overlayed with bss */ -static u32 wrsr __attribute__((section(".data"))); +static u32 wrsr __data; #define WRSR_POR (1 << 4) #define WRSR_TOUT (1 << 1) @@ -209,47 +289,97 @@ static void print_reset_cause(void) static const char __data *tx6_mod_suffix; -static void tx6qdl_print_cpuinfo(void) +#ifdef CONFIG_IMX6_THERMAL +#include +#include +#include + +static void print_temperature(void) +{ + struct udevice *thermal_dev; + int cpu_tmp, minc, maxc, ret; + char const *grade_str; + static u32 __data thermal_calib; + + puts("Temperature: "); + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + grade_str = "Automotive"; + break; + case TEMP_INDUSTRIAL: + grade_str = "Industrial"; + break; + case TEMP_EXTCOMMERCIAL: + grade_str = "Extended Commercial"; + break; + default: + grade_str = "Commercial"; + } + printf("%s grade (%dC to %dC)", grade_str, minc, maxc); + ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); + if (ret == 0) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + + if (ret == 0) + printf(" at %dC", cpu_tmp); + else + puts(" - failed to read sensor data"); + } else { + puts(" - no sensor device found"); + } + + if (fuse_read(1, 6, &thermal_calib) == 0) { + printf(" - calibration data 0x%08x\n", thermal_calib); + } else { + puts(" - Failed to read thermal calib fuse\n"); + } +} +#else +static inline void print_temperature(void) +{ +} +#endif + +int checkboard(void) { u32 cpurev = get_cpu_rev(); char *cpu_str = "?"; - switch ((cpurev >> 12) & 0xff) { - case MXC_CPU_MX6SL: + if (is_cpu_type(MXC_CPU_MX6SL)) { cpu_str = "SL"; tx6_mod_suffix = "?"; - break; - case MXC_CPU_MX6DL: + } else if (is_cpu_type(MXC_CPU_MX6DL)) { cpu_str = "DL"; tx6_mod_suffix = "U"; - break; - case MXC_CPU_MX6SOLO: + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { cpu_str = "SOLO"; tx6_mod_suffix = "S"; - break; - case MXC_CPU_MX6Q: + } else if (is_cpu_type(MXC_CPU_MX6Q)) { cpu_str = "Q"; tx6_mod_suffix = "Q"; - break; + } else if (is_cpu_type(MXC_CPU_MX6QP)) { + cpu_str = "QP"; + tx6_mod_suffix = "QP"; } - printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", + printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", cpu_str, (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + print_temperature(); print_reset_cause(); #ifdef CONFIG_MX6_TEMPERATURE_HOT check_cpu_temperature(1); #endif + tx6_i2c_recover(); + return 0; } +/* serial port not initialized at this point */ int board_early_init_f(void) { - gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); - imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); - return 0; } @@ -259,9 +389,113 @@ static bool tx6_temp_check_enabled = true; #define tx6_temp_check_enabled 0 #endif +#ifdef CONFIG_TX6_NAND +#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) +#else +#ifdef CONFIG_MMC_BOOT_SIZE +#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) +#else +#define TX6_FLASH_SZ 2 +#endif +#endif /* CONFIG_TX6_NAND */ + +#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1) + +static char tx6_mem_table[] = { + '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */ + '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */ + '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */ + '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */ + '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */ + '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */ + '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */ + '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */ + '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */ + '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */ + '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */ +#if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2 + '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */ +#else + '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */ +#endif +}; + +static struct { + uchar addr; + uchar rev; +} tx6_mod_revs[] = { + { 0x3c, 1, }, + { 0x32, 2, }, + { 0x33, 3, }, +}; + +static inline char tx6_mem_suffix(void) +{ + size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ; + + debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n", + TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx); + + if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) + return '?'; + if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512) + return '7'; + if (mem_idx == 8) + return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3'; + return tx6_mem_table[mem_idx]; +}; + +static int tx6_get_mod_rev(unsigned int pmic_id) +{ + if (pmic_id < ARRAY_SIZE(tx6_mod_revs)) + return tx6_mod_revs[pmic_id].rev; + + return 0; +} + +static int tx6_pmic_probe(void) +{ + int i; + + debug("%s@%d: \n", __func__, __LINE__); + + for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) { + u8 i2c_addr = tx6_mod_revs[i].addr; + int ret = i2c_probe(i2c_addr); + + if (ret == 0) { + debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr); + return i; + } + debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr); + } + return -EINVAL; +} + int board_init(void) { int ret; + int pmic_id; + + debug("%s@%d: \n", __func__, __LINE__); + + pmic_id = tx6_pmic_probe(); + if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs)) + pmic_addr = tx6_mod_revs[pmic_id].addr; + + printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", + tx6_mod_suffix, + is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8, + is_lvds(), tx6_get_mod_rev(pmic_id), + tx6_mem_suffix()); + + get_hab_status(); + + ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); + if (ret < 0) { + printf("Failed to request tx6qdl_gpios: %d\n", ret); + } + imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; @@ -275,12 +509,12 @@ int board_init(void) #ifndef CONFIG_MX6_TEMPERATURE_HOT tx6_temp_check_enabled = false; #endif - return 1; + return 0; } - ret = tx6_pmic_init(); + ret = tx6_pmic_init(pmic_addr, NULL, 0); if (ret) { - printf("Failed to setup PMIC voltages\n"); + printf("Failed to setup PMIC voltages: %d\n", ret); hang(); } return 0; @@ -288,14 +522,18 @@ int board_init(void) int dram_init(void) { + debug("%s@%d: \n", __func__, __LINE__); + /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); return 0; } void dram_init_banksize(void) { + debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__, + CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH); gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); @@ -306,8 +544,8 @@ void dram_init_banksize(void) #endif } -#ifdef CONFIG_CMD_MMC -#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ +#ifdef CONFIG_FSL_ESDHC +#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST) @@ -342,7 +580,8 @@ static const iomux_v3_cfg_t mmc3_pads[] = { MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* eMMC RESET */ - MX6_PAD_NANDF_ALE__SD4_RESET, + MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | + PAD_CTL_DSE_40ohm), }; #endif @@ -410,6 +649,8 @@ int board_mmc_init(bd_t *bis) { int i; + debug("%s@%d: \n", __func__, __LINE__); + for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) { struct mmc *mmc; struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i]; @@ -443,11 +684,6 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_FEC_MXC -#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) -#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - #ifndef ETH_ALEN #define ETH_ALEN 6 #endif @@ -456,6 +692,8 @@ int board_eth_init(bd_t *bis) { int ret; + debug("%s@%d: \n", __func__, __LINE__); + /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); @@ -476,8 +714,8 @@ static void tx6_init_mac(void) { u8 mac[ETH_ALEN]; - imx_get_mac_from_fuse(-1, mac); - if (!is_valid_ether_addr(mac)) { + imx_get_mac_from_fuse(0, mac); + if (!is_valid_ethaddr(mac)) { printf("No valid MAC address programmed\n"); return; } @@ -568,14 +806,12 @@ static const struct gpio stk5_gpios[] = { }; #ifdef CONFIG_LCD -static u16 tx6_cmap[256]; vidinfo_t panel_info = { /* set to max. size supported by SoC */ .vl_col = 1920, .vl_row = 1080, .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ - .cmap = tx6_cmap, }; static struct fb_videomode tx6_fb_modes[] = { @@ -645,7 +881,6 @@ static struct fb_videomode tx6_fb_modes[] = { .upper_margin = 2, .vsync_len = 10, .lower_margin = 2, - .sync = FB_SYNC_CLK_LAT_FALL, }, { /* Emerging ET0500G0DH6 800 x 480 display. @@ -764,9 +999,9 @@ void lcd_enable(void) */ lcd_is_enabled = 0; - karo_load_splashimage(1); - if (lcd_enabled) { + karo_load_splashimage(1); + debug("Switching LCD on\n"); gpio_set_value(TX6_LCD_PWR_GPIO, 1); udelay(100); @@ -859,6 +1094,7 @@ void lcd_ctrl_init(void *lcdbase) if (!lcd_enabled) { debug("LCD disabled\n"); + goto disable; return; } @@ -866,6 +1102,7 @@ void lcd_ctrl_init(void *lcdbase) debug("Disabling LCD\n"); lcd_enabled = 0; setenv("splashimage", NULL); + goto disable; return; } @@ -875,6 +1112,7 @@ void lcd_ctrl_init(void *lcdbase) if (video_mode == NULL) { debug("Disabling LCD\n"); lcd_enabled = 0; + goto disable; return; } vm = video_mode; @@ -888,6 +1126,7 @@ void lcd_ctrl_init(void *lcdbase) fb_mode.xres, fb_mode.yres, panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; + goto disable; return; } } @@ -979,12 +1218,14 @@ void lcd_ctrl_init(void *lcdbase) printf(" %s", p->name); } printf("\n"); + goto disable; return; } if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; + goto disable; return; } panel_info.vl_col = p->xres; @@ -1043,6 +1284,7 @@ void lcd_ctrl_init(void *lcdbase) lcd_enabled = 0; printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD", lcd_bus_width); + goto disable; return; } if (is_lvds()) { @@ -1054,6 +1296,7 @@ void lcd_ctrl_init(void *lcdbase) if (lvds_chan_mask == 0) { printf("No LVDS channel active\n"); lcd_enabled = 0; + goto disable; return; } @@ -1083,6 +1326,13 @@ void lcd_ctrl_init(void *lcdbase) } else { debug("Skipping initialization of LCD controller\n"); } + return; + +disable: + lcd_enabled = 0; + panel_info.vl_col = 0; + panel_info.vl_row = 0; + } #else #define lcd_enabled 0 @@ -1090,7 +1340,13 @@ void lcd_ctrl_init(void *lcdbase) static void stk5_board_init(void) { - gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + int ret; + + ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + if (ret < 0) { + printf("Failed to request stk5_gpios: %d\n", ret); + return; + } imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); } @@ -1101,10 +1357,17 @@ static void stk5v3_board_init(void) static void stk5v5_board_init(void) { + int ret; + stk5_board_init(); - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, + ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); + if (ret) { + printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret); + return; + } + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); } @@ -1131,9 +1394,10 @@ static void tx6qdl_set_cpu_clock(void) int board_late_init(void) { - int ret = 0; const char *baseboard; + debug("%s@%d: \n", __func__, __LINE__); + env_cleanup(); if (tx6_temp_check_enabled) @@ -1174,7 +1438,8 @@ int board_late_init(void) } else { printf("WARNING: Unsupported baseboard: '%s'\n", baseboard); - ret = -EINVAL; + if (!had_ctrlc()) + return -EINVAL; } exit: @@ -1182,89 +1447,6 @@ exit: gpio_set_value(TX6_RESET_OUT_GPIO, 1); clear_ctrlc(); - return ret; -} - -#ifdef CONFIG_TX6_NAND -#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) -#else -#ifdef CONFIG_MMC_BOOT_SIZE -#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) -#else -#define TX6_FLASH_SZ 2 -#endif -#endif /* CONFIG_TX6_NAND */ - -#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1) - -static char tx6_mem_table[] = { - '4', /* 256MiB SDRAM 16bit; 128MiB NAND */ - '1', /* 512MiB SDRAM 32bit; 128MiB NAND */ - '0', /* 1GiB SDRAM 64bit; 128MiB NAND */ - '?', /* 256MiB SDRAM 16bit; 256MiB NAND */ - '?', /* 512MiB SDRAM 32bit; 256MiB NAND */ - '2', /* 1GiB SDRAM 64bit; 256MiB NAND */ - '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */ - '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */ - '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */ - '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */ - '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */ - '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */ -}; - -static inline char tx6_mem_suffix(void) -{ - size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ; - - debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n", - TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx); - - if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) - return '?'; - - return tx6_mem_table[mem_idx]; -}; - -static struct { - uchar addr; - uchar rev; -} tx6_mod_revs[] = { - { 0x3c, 1, }, - { 0x32, 2, }, - { 0x33, 3, }, -}; - -static int tx6_get_mod_rev(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) { - int ret = i2c_probe(tx6_mod_revs[i].addr); - if (ret == 0) { - debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr); - return tx6_mod_revs[i].rev; - } - debug("I2C probe returned %d for addr %02x\n", ret, - tx6_mod_revs[i].addr); - } - return 0; -} - -int checkboard(void) -{ - u32 cpurev = get_cpu_rev(); - int cpu_variant = (cpurev >> 12) & 0xff; - - tx6qdl_print_cpuinfo(); - - i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */); - - printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", - tx6_mod_suffix, - cpu_variant == MXC_CPU_MX6Q ? 1 : 8, - is_lvds(), tx6_get_mod_rev(), - tx6_mem_suffix()); - return 0; } @@ -1312,7 +1494,6 @@ int ft_board_setup(void *blob, bd_t *bd) karo_fdt_enable_node(blob, "stk5led", 0); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - fdt_fixup_ethernet(blob); karo_fdt_fixup_touchpanel(blob, tx6_touchpanels, ARRAY_SIZE(tx6_touchpanels));