X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6ul_ll_init.S;h=0e15109deada439218254873469ae254ff7e830f;hp=299e469d7b70e8ba810cce98c43003262602d6eb;hb=02e0d243b17007d5248df08260163ee6e706aad7;hpb=ddc2d056e83d1a88dd24a5e03e7460dc37f2f423 diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S index 299e469d7b..0e15109dea 100644 --- a/board/karo/tx6/tx6ul_ll_init.S +++ b/board/karo/tx6/tx6ul_ll_init.S @@ -22,6 +22,8 @@ #define SDRAM_SIZE PHYS_SDRAM_1_SIZE #endif +#define CCGR(m) (3 << ((m) * 2)) + #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ @@ -92,6 +94,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max @@ -131,7 +134,7 @@ dcd_end: #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ /* DDR3 SDRAM */ -#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE +#ifdef PHYS_SDRAM_2_SIZE #define BANK_ADDR_BITS 2 #else #define BANK_ADDR_BITS 1 @@ -163,6 +166,11 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE <= SZ_256M +/* 256MiB SDRAM: NT5CB128M16FP-DII */ +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -186,6 +194,35 @@ CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */ CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ +#else +/* 512MiB SDRAM: IM4G16D3EABG-125I */ +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +#endif /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ @@ -225,9 +262,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 @@ -546,24 +580,22 @@ dcd_hdr: MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9) - /* ENET_REF_CLK */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000000b1) - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000000b1) - MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2) - MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2) - /* ETN PHY nRST */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6, 0x00000015) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6, 0x000010b0) - /* ETN PHY Power */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0) +#ifndef CONFIG_TX6_EMMC + /* switch NFC clock to 99MHz */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */ -#define CCGR(m) (3 << ((m) * 2)) + /* enable all relevant clocks... */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) /* enable UART clock depending on selected console port */ @@ -581,7 +613,11 @@ dcd_hdr: MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */ // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */ // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */ +#ifdef CONFIG_SOC_MX6ULL + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(6)) /* default: 0xcfc03f0f ENET */ +#else MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */ +#endif #ifdef CONFIG_TX6_NAND MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */ @@ -592,7 +628,6 @@ dcd_hdr: #else MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */ #endif - MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(0x020c80b0, 0)