X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=drivers%2Fnet%2Ffec_mxc.c;h=343646c939b51f0389d69235f2374ad5ca074638;hp=7e2721070efd478f5ec05ccc2f3785b893dec346;hb=b4e7ee80e7b4401b991206dfbee183af69f64344;hpb=ef8e3a3bbf0720068b7bf6e4f182c17679f94fa2 diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 7e2721070e..343646c939 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -5,34 +5,24 @@ * (C) Copyright 2007 Pengutronix, Sascha Hauer * (C) Copyright 2007 Pengutronix, Juergen Beisert * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include -#include "fec_mxc.h" +#include #include #include #include #include #include +#include "fec_mxc.h" + DECLARE_GLOBAL_DATA_PTR; /* @@ -41,6 +31,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000 +/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -53,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; * The i.MX28 operates with packets in big endian. We need to swap them before * sending and after receiving. */ -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 #define CONFIG_FEC_MXC_SWAP_PACKET #endif @@ -71,13 +69,6 @@ DECLARE_GLOBAL_DATA_PTR; #undef DEBUG -struct nbuf { - uint8_t data[1500]; /**< actual data */ - int length; /**< actual length */ - int used; /**< buffer in use or not */ - uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ -}; - #ifdef CONFIG_FEC_MXC_SWAP_PACKET static void swap_packet(uint32_t *packet, int length) { @@ -96,7 +87,7 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ - uint32_t start; + ulong start; int val; /* @@ -116,6 +107,8 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + if (readl(ð->ievent) & FEC_IEVENT_MII) + break; printf("Read MDIO failed...\n"); return -1; } @@ -130,7 +123,7 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, * it's now safe to read the PHY's register */ val = (unsigned short)readl(ð->mii_data); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, + debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr, regAddr, val); return val; } @@ -141,8 +134,12 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, - ð->mii_speed); + register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); +#ifdef FEC_QUIRK_ENET_MAC + speed--; +#endif + speed <<= 1; + writel(speed, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } @@ -151,7 +148,7 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ - uint32_t start; + ulong start; reg = regAddr << FEC_MII_DATA_RA_SHIFT; phy = phyAddr << FEC_MII_DATA_PA_SHIFT; @@ -165,6 +162,8 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + if (readl(ð->ievent) & FEC_IEVENT_MII) + break; printf("Write MDIO failed...\n"); return -1; } @@ -174,19 +173,20 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, * clear MII interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, + debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr, regAddr, data); return 0; } -int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) +static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr) { return fec_mdio_read(bus->priv, phyAddr, regAddr); } -int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, - u16 data) +static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr, u16 data) { return fec_mdio_write(bus->priv, phyAddr, regAddr, data); } @@ -203,7 +203,7 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ -#ifdef CONFIG_MX27 +#ifdef CONFIG_SOC_MX27 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); #endif fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); @@ -254,26 +254,22 @@ static int miiphy_wait_aneg(struct eth_device *dev) } #endif -static int fec_rx_task_enable(struct fec_priv *fec) +static inline void fec_rx_task_enable(struct fec_priv *fec) { - writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); - return 0; + writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->r_des_active); } -static int fec_rx_task_disable(struct fec_priv *fec) +static inline void fec_rx_task_disable(struct fec_priv *fec) { - return 0; } -static int fec_tx_task_enable(struct fec_priv *fec) +static inline void fec_tx_task_enable(struct fec_priv *fec) { writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); - return 0; } -static int fec_tx_task_disable(struct fec_priv *fec) +static inline void fec_tx_task_disable(struct fec_priv *fec) { - return 0; } /** @@ -283,49 +279,34 @@ static int fec_tx_task_disable(struct fec_priv *fec) * @param[in] dsize desired size of each receive buffer * @return 0 on success * - * For this task we need additional memory for the data buffers. And each - * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each. + * Init all RX descriptors to default values. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; + uint8_t *data; int i; /* - * Allocate memory for the buffers. This allocation respects the - * alignment + * Reload the RX descriptors with default values and wipe + * the RX buffers. */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - if (data_ptr == 0) { - uint8_t *data = memalign(ARCH_DMA_MINALIGN, - size); - if (!data) { - printf("%s: error allocating rxbuf %d\n", - __func__, i); - goto err; - } - writel((uint32_t)data, &fec->rbd_base[i].data_pointer); - } /* needs allocation */ - writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); - writew(0, &fec->rbd_base[i].data_length); + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; } /* Mark the last RBD to close the ring. */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - return 0; - -err: - for (; i >= 0; i--) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - free((void *)data_ptr); - } - - return -ENOMEM; + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); } /** @@ -345,10 +326,12 @@ static void fec_tbd_init(struct fec_priv *fec) unsigned addr = (unsigned)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - writew(0x0000, &fec->tbd_base[0].status); - writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; fec->tbd_index = 0; - flush_dcache_range(addr, addr+size); + flush_dcache_range(addr, addr + size); } /** @@ -369,7 +352,7 @@ static int fec_get_hwaddr(struct eth_device *dev, int dev_id, unsigned char *mac) { imx_get_mac_from_fuse(dev_id, mac); - return !is_valid_ether_addr(mac); + return !is_valid_ethaddr(mac); } static int fec_set_hwaddr(struct eth_device *dev) @@ -392,21 +375,6 @@ static int fec_set_hwaddr(struct eth_device *dev) return 0; } -static void fec_eth_phy_config(struct eth_device *dev) -{ -#ifdef CONFIG_PHYLIB - struct fec_priv *fec = (struct fec_priv *)dev->priv; - struct phy_device *phydev; - - phydev = phy_connect(fec->bus, fec->phy_id, dev, - PHY_INTERFACE_MODE_RGMII); - if (phydev) { - fec->phydev = phydev; - phy_config(phydev); - } -#endif -} - /* * Do initial configuration of the FEC registers */ @@ -447,7 +415,7 @@ static void fec_reg_setup(struct fec_priv *fec) */ static int fec_open(struct eth_device *edev) { - struct fec_priv *fec = (struct fec_priv *)edev->priv; + struct fec_priv *fec = edev->priv; int speed; uint32_t addr, size; int i; @@ -481,7 +449,7 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL) udelay(100); /* * setup the MII gasket for RMII mode @@ -511,9 +479,7 @@ static int fec_open(struct eth_device *edev) #endif #ifdef CONFIG_PHYLIB - if (!fec->phydev) - fec_eth_phy_config(edev); - if (fec->phydev) { + { /* Start up the PHY */ int ret = phy_startup(fec->phydev); @@ -523,8 +489,6 @@ static int fec_open(struct eth_device *edev) return ret; } speed = fec->phydev->speed; - } else { - speed = _100BASET; } #else miiphy_wait_aneg(edev); @@ -535,9 +499,8 @@ static int fec_open(struct eth_device *edev) #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; - u32 rcr = (readl(&fec->eth->r_cntrl) & - ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | - FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; + u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; + if (speed == _1000BASET) ecr |= FEC_ECNTRL_SPEED; else if (speed != _100BASET) @@ -545,6 +508,14 @@ static int fec_open(struct eth_device *edev) writel(ecr, &fec->eth->ecntrl); writel(rcr, &fec->eth->r_cntrl); } +#elif defined(CONFIG_SOC_MX28) + { + u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; + + if (speed == _10BASET) + rcr |= FEC_RCNTRL_RMII_10T; + writel(rcr, &fec->eth->r_cntrl); + } #endif debug("%s:Speed=%i\n", __func__, speed); @@ -553,60 +524,26 @@ static int fec_open(struct eth_device *edev) */ fec_rx_task_enable(fec); - udelay(100000); +// udelay(100000); return 0; } static int fec_init(struct eth_device *dev, bd_t* bd) { - struct fec_priv *fec = (struct fec_priv *)dev->priv; - uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; - uint32_t size; - int i, ret; + struct fec_priv *fec = dev->priv; + uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * Allocate transmit descriptors, there are two in total. This - * allocation respects cache alignment. + * Setup transmit descriptors, there are two in total. */ - if (!fec->tbd_base) { - size = roundup(2 * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->tbd_base) { - ret = -ENOMEM; - goto err1; - } - memset(fec->tbd_base, 0, size); - fec_tbd_init(fec); - flush_dcache_range((unsigned)fec->tbd_base, size); - } + fec_tbd_init(fec); - /* - * Allocate receive descriptors. This allocation respects cache - * alignment. - */ - if (!fec->rbd_base) { - size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->rbd_base) { - ret = -ENOMEM; - goto err2; - } - memset(fec->rbd_base, 0, size); - /* - * Initialize RxBD ring - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - ret = -ENOMEM; - goto err3; - } - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); - } + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); fec_reg_setup(fec); @@ -626,8 +563,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd) /* clear MIB RAM */ - for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) - writel(0, i); + for (i = 0; i <= 0xfc >> 2; i++) + writel(0, &mib_ptr[i]); /* FIFO receive start register */ writel(0x520, &fec->eth->r_fstart); @@ -643,13 +580,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) #endif fec_open(dev); return 0; - -err3: - free(fec->rbd_base); -err2: - free(fec->tbd_base); -err1: - return ret; } /** @@ -659,7 +589,7 @@ err1: static void fec_halt(struct eth_device *dev) { struct fec_priv *fec = (struct fec_priv *)dev->priv; - int counter = 0xffff; + int counter = 1000; /* * issue graceful stop command to the FEC transmitter if necessary @@ -672,7 +602,7 @@ static void fec_halt(struct eth_device *dev) * wait for graceful stop to register */ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) - udelay(1); + udelay(100); /* * Disable SmartDMA tasks @@ -710,7 +640,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * This routine transmits one frame. This routine only accepts * 6-byte Ethernet addresses. */ - struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct fec_priv *fec = dev->priv; /* * Check for valid length of data. @@ -735,13 +665,14 @@ static int fec_send(struct eth_device *dev, void *packet, int length) flush_dcache_range(addr, end); writew(length, &fec->tbd_base[fec->tbd_index].data_length); - writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); + writel((unsigned long)packet, + &fec->tbd_base[fec->tbd_index].data_pointer); /* * update BD's status now * This block: * - is always the last in a chain (means no chain) - * - should transmitt the CRC + * - should transmit the CRC * - might be the last BD in the list, so the address counter should * wrap (-> keep the WRAP flag) */ @@ -758,6 +689,28 @@ static int fec_send(struct eth_device *dev, void *packet, int length) addr = (uint32_t)fec->tbd_base; flush_dcache_range(addr, addr + size); + /* + * Below we read the DMA descriptor's last four bytes back from the + * DRAM. This is important in order to make sure that all WRITE + * operations on the bus that were triggered by previous cache FLUSH + * have completed. + * + * Otherwise, on MX28, it is possible to observe a corruption of the + * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM + * for the bus structure of MX28. The scenario is as follows: + * + * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going + * to DRAM due to flush_dcache_range() + * 2) ARM core writes the FEC registers via AHB_ARB2 + * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 + * + * Note that 2) does sometimes finish before 1) due to reordering of + * WRITE accesses on the AHB bus, therefore triggering 3) before the + * DMA descriptor is fully written into DRAM. This results in occasional + * corruption of the DMA descriptor. + */ + readl(addr + size - 4); + /* * Enable SmartDMA transmit task */ @@ -773,13 +726,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; } - if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + } - invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & + FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL; +out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret); @@ -803,18 +780,20 @@ static int fec_recv(struct eth_device *dev) struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; unsigned long ievent; int frame_length, len = 0; - struct nbuf *frame; uint16_t bd_status; uint32_t addr, size, end; int i; - uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); + ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); /* * Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); - writel(ievent, &fec->eth->ievent); - debug("fec_recv: ievent 0x%lx\n", ievent); + if (ievent) + writel(ievent, &fec->eth->ievent); + + if (ievent) + debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { fec_halt(dev); fec_init(dev, fec->bd); @@ -855,20 +834,20 @@ static int fec_recv(struct eth_device *dev) invalidate_dcache_range(addr, addr + size); bd_status = readw(&rbd->status); - debug("fec_recv: status 0x%x\n", bd_status); - if (!(bd_status & FEC_RBD_EMPTY)) { + debug("fec_recv: status 0x%04x len %u\n", bd_status, + readw(&rbd->data_length) - 4); if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && ((readw(&rbd->data_length) - 4) > 14)) { /* * Get buffer address and size */ - frame = (struct nbuf *)readl(&rbd->data_pointer); + addr = readl(&rbd->data_pointer); frame_length = readw(&rbd->data_length) - 4; + /* * Invalidate data cache over the buffer */ - addr = (uint32_t)frame; end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); addr &= ~(ARCH_DMA_MINALIGN - 1); invalidate_dcache_range(addr, end); @@ -877,16 +856,15 @@ static int fec_recv(struct eth_device *dev) * Fill the buffer and pass it to upper layers */ #ifdef CONFIG_FEC_MXC_SWAP_PACKET - swap_packet((uint32_t *)frame->data, frame_length); + swap_packet((uint32_t *)addr, frame_length); #endif - memcpy(buff, frame->data, frame_length); - NetReceive(buff, frame_length); + memcpy(buff, (char *)addr, frame_length); + net_process_received_packet(buff, frame_length); len = frame_length; } else { if (bd_status & FEC_RBD_ERR) - printf("error frame: 0x%08lx 0x%08x\n", - (ulong)rbd->data_pointer, - bd_status); + printf("error frame: 0x%08x 0x%08x\n", + addr, bd_status); } /* @@ -909,8 +887,8 @@ static int fec_recv(struct eth_device *dev) fec_rx_task_enable(fec); fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; + debug("fec_recv: stop\n"); } - debug("fec_recv: stop\n"); return len; } @@ -920,32 +898,106 @@ static void fec_set_dev_name(char *dest, int dev_id) sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); } -static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(FEC_DMA_RX_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + +#ifdef CONFIG_PHYLIB +int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, + struct mii_dev *bus, struct phy_device *phydev) +#else +static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, + struct mii_dev *bus, int phy_id) +#endif { struct eth_device *edev; struct fec_priv *fec; - struct mii_dev *bus; unsigned char ethaddr[6]; uint32_t start; int ret = 0; /* create and fill edev struct */ - edev = (struct eth_device *)malloc(sizeof(struct eth_device)); + edev = calloc(sizeof(struct eth_device), 1); if (!edev) { puts("fec_mxc: not enough malloc memory for eth_device\n"); ret = -ENOMEM; goto err1; } - fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); + fec = calloc(sizeof(struct fec_priv), 1); if (!fec) { puts("fec_mxc: not enough malloc memory for fec_priv\n"); ret = -ENOMEM; goto err2; } - memset(edev, 0, sizeof(*edev)); - memset(fec, 0, sizeof(*fec)); + ret = fec_alloc_descs(fec); + if (ret) + goto err3; edev->priv = fec; edev->init = fec_init; @@ -965,54 +1017,38 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); - goto err3; + goto err4; } udelay(10); } fec_reg_setup(fec); - fec_set_dev_name(edev->name, dev_id); fec->dev_id = (dev_id == -1) ? 0 : dev_id; - fec->phy_id = phy_id; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - ret = -ENOMEM; - goto err3; - } - bus->read = fec_phy_read; - bus->write = fec_phy_write; - fec_set_dev_name(bus->name, dev_id); -#ifdef CONFIG_MX28 - /* - * The i.MX28 has two ethernet interfaces, but they are not equal. - * Only the first one can access the MDIO bus. - */ - bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; + fec->bus = bus; + fec_mii_setspeed(bus->priv); +#ifdef CONFIG_PHYLIB + fec->phydev = phydev; + phy_connect_dev(phydev, edev); + /* Configure phy */ + phy_config(phydev); #else - bus->priv = fec->eth; + fec->phy_id = phy_id; #endif - fec_mii_setspeed(bus->priv); - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - ret = -ENOMEM; - goto err3; - } - fec->bus = bus; eth_register(edev); if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { - debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); + if (dev_id < 0) + debug("got MAC address from fuse: %pM\n", ethaddr); + else + debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", ethaddr); } - /* Configure phy */ - fec_eth_phy_config(edev); return ret; - +err4: + fec_free_descs(fec); err3: free(fec); err2: @@ -1021,10 +1057,72 @@ err1: return ret; } +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) +{ + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return NULL; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + bus->priv = eth; + fec_set_dev_name(bus->name, dev_id); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return NULL; + } + fec_mii_setspeed(eth); + return bus; +} + int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) { + uint32_t base_mii; + struct mii_dev *bus = NULL; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev = NULL; +#endif + int ret; + +#ifdef CONFIG_SOC_MX28 + /* + * The i.MX28 has two ethernet interfaces, but they are not equal. + * Only the first one can access the MDIO bus. + */ + base_mii = MXS_ENET0_BASE; +#else + base_mii = addr; +#endif debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); - return fec_probe(bd, dev_id, phy_id, addr); + bus = fec_get_miibus(base_mii, dev_id); + if (!bus) + return -ENOMEM; +#ifdef CONFIG_PHYLIB + phydev = phy_find_by_mask(bus, phy_id < 0 ? 0xff : (1 << phy_id), + PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return -ENOMEM; + } + ret = fec_probe(bd, dev_id, addr, bus, phydev); +#else + ret = fec_probe(bd, dev_id, addr, bus, phy_id); +#endif + if (ret) { +#ifdef CONFIG_PHYLIB + free(phydev); +#endif + free(bus); + } + return ret; } #ifdef CONFIG_FEC_MXC_PHYADDR