X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=drivers%2Fnet%2Fsh_eth.c;h=bb57e4d53a03a2c82f326479bdd6893d475456a3;hp=9e3cf98b3b633191efb780ca44dab5a240101516;hb=4398d55991eb3c2484a2a8e991d701e5d7a64874;hpb=859f24350e6e4313626f85161dd03f025a4dac59 diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 9e3cf98b3b..bb57e4d53a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1,8 +1,8 @@ /* * sh_eth.c - Driver for Renesas SH7763's ethernet controler. * - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008, 2011 Renesas Solutions Corp. + * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu * Copyright (c) 2007 Carlos Munoz * * This program is free software; you can redistribute it and/or modify @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include @@ -35,177 +37,36 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif +#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK +#define flush_cache_wback(addr, len) \ + dcache_wback_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif -extern int eth_init(bd_t *bd); -extern void eth_halt(void); -extern int eth_rx(void); -extern int eth_send(volatile void *packet, int length); - -static struct dev_info_s *dev; - -/* - * Bits are written to the PHY serially using the - * PIR register, just like a bit banger. - */ -static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) -{ - int i; - u32 pir; - - /* Bit positions is 1 less than the number of bits */ - for (i = len - 1; i >= 0; i--) { - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is high */ - pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - } -} - -static void sh_eth_mii_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} - -static void sh_eth_mii_ind_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} - -static int sh_eth_mii_read_phy_bits(int port, u32 * val, int len) -{ - int i; - u32 pir; - - *val = 0; - for (i = len - 1; i >= 0; i--) { - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read bit */ - pir = inl(PIR(port)); - *val |= (pir & 8) ? 1 << i : 0; - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); - } - - return 0; -} - -#define PHY_INIT 0xFFFFFFFF -#define PHY_READ 0x02 -#define PHY_WRITE 0x01 -/* - * To read a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (Bus release): - * data (16 bits): read data - */ -static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) -{ - u32 val; - - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - - /* Bus release */ - sh_eth_mii_bus_release(port); - - /* Read register */ - sh_eth_mii_read_phy_bits(port, &val, 16); - - return val; -} +#define TIMEOUT_CNT 1000 -/* - * To write a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (2 bits): 10 - * data (16 bits): write data - * idle (Independent bus release) - */ -static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) +int sh_eth_send(struct eth_device *dev, void *packet, int len) { - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - /* ta */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* Write register data */ - sh_eth_mii_write_phy_bits(port, val, 16); - - /* Independent bus release */ - sh_eth_mii_ind_bus_release(port); -} - -void eth_halt(void) -{ -} - -int eth_send(volatile void *packet, int len) -{ - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; - int timeout; - int rc = 0; + struct sh_eth_dev *eth = dev->priv; + int port = eth->port, ret = 0, timeout; + struct sh_eth_info *port_info = ð->port_info[port]; if (!packet || len > 0xffff) { - printf("eth_send: Invalid argument\n"); - return -EINVAL; + printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); + ret = -EINVAL; + goto err; } /* packet must be a 4 byte boundary */ - if ((int)packet & (4 - 1)) { - printf("eth_send: packet not 4 byte alligned\n"); - return -EFAULT; + if ((int)packet & 3) { + printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); + ret = -EFAULT; + goto err; } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); port_info->tx_desc_cur->td1 = len << 16; /* Must preserve the end of descriptor list indication */ @@ -219,38 +80,38 @@ int eth_send(volatile void *packet, int len) outl(EDTRR_TRNS, EDTRR(port)); /* Wait until packet is transmitted */ - timeout = 1000; + timeout = TIMEOUT_CNT; while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) udelay(100); if (timeout < 0) { - printf("eth_send: transmit timeout\n"); - rc = -1; + printf(SHETHER_NAME ": transmit timeout\n"); + ret = -ETIMEDOUT; goto err; } -err: port_info->tx_desc_cur++; if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) port_info->tx_desc_cur = port_info->tx_desc_base; - return rc; +err: + return ret; } -int eth_rx(void) +int sh_eth_recv(struct eth_device *dev) { - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; - int len = 0; - volatile u8 *packet; + struct sh_eth_dev *eth = dev->priv; + int port = eth->port, len = 0; + struct sh_eth_info *port_info = ð->port_info[port]; + uchar *packet; /* Check if the rx descriptor is ready */ if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { /* Check for errors */ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { len = port_info->rx_desc_cur->rd1 & 0xffff; - packet = (volatile u8 *) - ADDR_TO_P2(port_info->rx_desc_cur->rd2); + packet = (uchar *) + ADDR_TO_P2(port_info->rx_desc_cur->rd2); NetReceive(packet, len); } @@ -274,51 +135,62 @@ int eth_rx(void) return len; } -#define EDMR_INIT_CNT 1000 -static int sh_eth_reset(struct dev_info_s *dev) +static int sh_eth_reset(struct sh_eth_dev *eth) { - int port = dev->port; - int i; + int port = eth->port; +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) + int ret = 0, i; /* Start e-dmac transmitter and receiver */ outl(EDSR_ENALL, EDSR(port)); /* Perform a software reset and wait for it to complete */ outl(EDMR_SRST, EDMR(port)); - for (i = 0; i < EDMR_INIT_CNT; i++) { + for (i = 0; i < TIMEOUT_CNT ; i++) { if (!(inl(EDMR(port)) & EDMR_SRST)) break; udelay(1000); } - if (i == EDMR_INIT_CNT) { - printf("Error: Software reset timeout\n"); - return -1; + if (i == TIMEOUT_CNT) { + printf(SHETHER_NAME ": Software reset timeout\n"); + ret = -EIO; } + + return ret; +#else + outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port)); + udelay(3000); + outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port)); + return 0; +#endif } -static int sh_eth_tx_desc_init(struct dev_info_s *dev) +static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) { - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; + int port = eth->port, i, ret = 0; u32 tmp_addr; + struct sh_eth_info *port_info = ð->port_info[port]; struct tx_desc_s *cur_tx_desc; - int i; - /* Allocate tx descriptors. They must be TX_DESC_SIZE bytes - aligned */ - if (!(port_info->tx_desc_malloc = malloc(NUM_TX_DESC * + /* + * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned + */ + port_info->tx_desc_malloc = malloc(NUM_TX_DESC * sizeof(struct tx_desc_s) + - TX_DESC_SIZE - 1))) { - printf("Error: malloc failed\n"); - return -ENOMEM; + TX_DESC_SIZE - 1); + if (!port_info->tx_desc_malloc) { + printf(SHETHER_NAME ": malloc failed\n"); + ret = -ENOMEM; + goto err; } + tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & ~(TX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); - port_info->tx_desc_cur = port_info->tx_desc_base; /* Initialize all descriptors */ @@ -336,46 +208,55 @@ static int sh_eth_tx_desc_init(struct dev_info_s *dev) /* Point the controller to the tx descriptor list. Must use physical addresses */ outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); outl(0x01, TDFFR(port));/* Last discriptor bit */ +#endif - return 0; +err: + return ret; } -static int sh_eth_rx_desc_init(struct dev_info_s *dev) +static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) { - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; - u32 tmp_addr; + int port = eth->port, i , ret = 0; + struct sh_eth_info *port_info = ð->port_info[port]; struct rx_desc_s *cur_rx_desc; + u32 tmp_addr; u8 *rx_buf; - int i; - /* Allocate rx descriptors. They must be RX_DESC_SIZE bytes - aligned */ - if (!(port_info->rx_desc_malloc = malloc(NUM_RX_DESC * + /* + * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned + */ + port_info->rx_desc_malloc = malloc(NUM_RX_DESC * sizeof(struct rx_desc_s) + - RX_DESC_SIZE - 1))) { - printf("Error: malloc failed\n"); - return -ENOMEM; + RX_DESC_SIZE - 1); + if (!port_info->rx_desc_malloc) { + printf(SHETHER_NAME ": malloc failed\n"); + ret = -ENOMEM; + goto err; } + tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & ~(RX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); port_info->rx_desc_cur = port_info->rx_desc_base; - /* Allocate rx data buffers. They must be 32 bytes aligned and in - P2 area */ - if (!(port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + - 31))) { - printf("Error: malloc failed\n"); - free(port_info->rx_desc_malloc); - port_info->rx_desc_malloc = NULL; - return -ENOMEM; + /* + * Allocate rx data buffers. They must be 32 bytes aligned and in + * P2 area + */ + port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); + if (!port_info->rx_buf_malloc) { + printf(SHETHER_NAME ": malloc failed\n"); + ret = -ENOMEM; + goto err_buf_malloc; } + tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & ~(32 - 1)); port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); @@ -395,22 +276,37 @@ static int sh_eth_rx_desc_init(struct dev_info_s *dev) /* Point the controller to the rx descriptor list */ outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); outl(RDFFR_RDLF, RDFFR(port)); +#endif - return 0; + return ret; + +err_buf_malloc: + free(port_info->rx_desc_malloc); + port_info->rx_desc_malloc = NULL; + +err: + return ret; } -static void sh_eth_desc_free(struct dev_info_s *dev) +static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) { - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; + int port = eth->port; + struct sh_eth_info *port_info = ð->port_info[port]; if (port_info->tx_desc_malloc) { free(port_info->tx_desc_malloc); port_info->tx_desc_malloc = NULL; } +} + +static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) +{ + int port = eth->port; + struct sh_eth_info *port_info = ð->port_info[port]; if (port_info->rx_desc_malloc) { free(port_info->rx_desc_malloc); @@ -423,67 +319,49 @@ static void sh_eth_desc_free(struct dev_info_s *dev) } } -static int sh_eth_desc_init(struct dev_info_s *dev) +static int sh_eth_desc_init(struct sh_eth_dev *eth) { - int rc; + int ret = 0; - if ((rc = sh_eth_tx_desc_init(dev)) || (rc = sh_eth_rx_desc_init(dev))) { - sh_eth_desc_free(dev); - return rc; - } + ret = sh_eth_tx_desc_init(eth); + if (ret) + goto err_tx_init; - return 0; -} + ret = sh_eth_rx_desc_init(eth); + if (ret) + goto err_rx_init; -static int sh_eth_phy_config(struct dev_info_s *dev) -{ - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; - int timeout; - u32 val; - /* Reset phy */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); - timeout = 10; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, PHY_CTRL); - if (!(val & PHY_C_RESET)) - break; - udelay(50000); - } - if (timeout < 0) { - printf("%s phy reset timeout\n", __func__); - return -1; - } + return ret; +err_rx_init: + sh_eth_tx_desc_free(eth); - /* Advertise 100/10 baseT full/half duplex */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, - (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); - /* Autonegotiation, normal operation, full duplex, enable tx */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, - (PHY_C_ANEGEN|PHY_C_RANEG)); - /* Wait for autonegotiation to complete */ - timeout = 100; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); - if (val & PHY_S_ANEGC) - break; - udelay(50000); - } - if (timeout < 0) { - printf("sh_eth_phy_config() phy auto-negotiation failed\n"); - return -1; - } +err_tx_init: + return ret; +} - return 0; +static int sh_eth_phy_config(struct sh_eth_dev *eth) +{ + int port = eth->port, ret = 0; + struct sh_eth_info *port_info = ð->port_info[port]; + struct eth_device *dev = port_info->dev; + struct phy_device *phydev; + + phydev = phy_connect( + miiphy_get_dev_by_name(dev->name), + port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); + port_info->phydev = phydev; + phy_config(phydev); + + return ret; } -static int sh_eth_config(struct dev_info_s *dev, bd_t * bd) +static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { - int port = dev->port; - struct port_info_s *port_info = &dev->port_info[port]; + int port = eth->port, ret = 0; u32 val; - u32 phy_status; - int rc; + struct sh_eth_info *port_info = ð->port_info[port]; + struct eth_device *dev = port_info->dev; + struct phy_device *phy; /* Configure e-dmac registers */ outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); @@ -492,112 +370,280 @@ static int sh_eth_config(struct dev_info_s *dev, bd_t * bd) outl(0, TFTR(port)); outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); outl(RMCR_RST, RMCR(port)); +#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) outl(0, RPADIR(port)); +#endif outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); /* Configure e-mac registers */ +#if defined(CONFIG_CPU_SH7757) + outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | + ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port)); +#else outl(0, ECSIPR(port)); +#endif /* Set Mac address */ - val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | - bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; + val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | + dev->enetaddr[2] << 8 | dev->enetaddr[3]; outl(val, MAHR(port)); - val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; + val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; outl(val, MALR(port)); outl(RFLR_RFL_MIN, RFLR(port)); +#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) outl(0, PIPR(port)); +#endif +#if !defined(CONFIG_CPU_SH7724) outl(APR_AP, APR(port)); outl(MPR_MP, MPR(port)); +#endif +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(TPAUSER_TPAUSE, TPAUSER(port)); +#elif defined(CONFIG_CPU_SH7757) + outl(TPAUSER_UNLIMITED, TPAUSER(port)); +#endif +#if defined(CONFIG_CPU_SH7734) + outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port)); +#endif /* Configure phy */ - if ((rc = sh_eth_phy_config(dev))) - return rc; + ret = sh_eth_phy_config(eth); + if (ret) { + printf(SHETHER_NAME ": phy config timeout\n"); + goto err_phy_cfg; + } + phy = port_info->phydev; + phy_startup(phy); - /* Read phy status to finish configuring the e-mac */ - phy_status = sh_eth_mii_read_phy_reg(dev->port, - dev->port_info[dev->port].phy_addr, - 1); + val = 0; /* Set the transfer speed */ - if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { - printf("100Base/"); + if (phy->speed == 100) { + printf(SHETHER_NAME ": 100Base/"); +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(GECMR_100B, GECMR(port)); - } else { - printf("10Base/"); +#elif defined(CONFIG_CPU_SH7757) + outl(1, RTRATE(port)); +#elif defined(CONFIG_CPU_SH7724) + val = ECMR_RTM; +#endif + } else if (phy->speed == 10) { + printf(SHETHER_NAME ": 10Base/"); +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(GECMR_10B, GECMR(port)); +#elif defined(CONFIG_CPU_SH7757) + outl(0, RTRATE(port)); +#endif } +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) + else if (phy->speed == 1000) { + printf(SHETHER_NAME ": 1000Base/"); + outl(GECMR_1000B, GECMR(port)); + } +#endif /* Check if full duplex mode is supported by the phy */ - if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { + if (phy->duplex) { printf("Full\n"); - outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); } else { printf("Half\n"); - outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); } - return 0; + + return ret; + +err_phy_cfg: + return ret; } -static int sh_eth_start(struct dev_info_s *dev) +static void sh_eth_start(struct sh_eth_dev *eth) { /* * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit */ - outl(EDRRR_R, EDRRR(dev->port)); + outl(EDRRR_R, EDRRR(eth->port)); +} - return 0; +static void sh_eth_stop(struct sh_eth_dev *eth) +{ + outl(~EDRRR_R, EDRRR(eth->port)); } -static int sh_eth_get_mac(bd_t *bd) +int sh_eth_init(struct eth_device *dev, bd_t *bd) { - char *s, *e; - int i; - - s = getenv("ethaddr"); - if (s != NULL) { - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - } else { - puts("Please set MAC address\n"); + int ret = 0; + struct sh_eth_dev *eth = dev->priv; + + ret = sh_eth_reset(eth); + if (ret) + goto err; + + ret = sh_eth_desc_init(eth); + if (ret) + goto err; + + ret = sh_eth_config(eth, bd); + if (ret) + goto err_config; + + sh_eth_start(eth); + + return ret; + +err_config: + sh_eth_tx_desc_free(eth); + sh_eth_rx_desc_free(eth); + +err: + return ret; +} + +void sh_eth_halt(struct eth_device *dev) +{ + struct sh_eth_dev *eth = dev->priv; + sh_eth_stop(eth); +} + +int sh_eth_initialize(bd_t *bd) +{ + int ret = 0; + struct sh_eth_dev *eth = NULL; + struct eth_device *dev = NULL; + + eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); + if (!eth) { + printf(SHETHER_NAME ": %s: malloc failed\n", __func__); + ret = -ENOMEM; + goto err; + } + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) { + printf(SHETHER_NAME ": %s: malloc failed\n", __func__); + ret = -ENOMEM; + goto err; } + memset(dev, 0, sizeof(struct eth_device)); + memset(eth, 0, sizeof(struct sh_eth_dev)); + + eth->port = CONFIG_SH_ETHER_USE_PORT; + eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + + dev->priv = (void *)eth; + dev->iobase = 0; + dev->init = sh_eth_init; + dev->halt = sh_eth_halt; + dev->send = sh_eth_send; + dev->recv = sh_eth_recv; + eth->port_info[eth->port].dev = dev; + + sprintf(dev->name, SHETHER_NAME); + + /* Register Device to EtherNet subsystem */ + eth_register(dev); + + bb_miiphy_buses[0].priv = eth; + miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); + + if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) + puts("Please set MAC address\n"); + + return ret; + +err: + if (dev) + free(dev); + + if (eth) + free(eth); + + printf(SHETHER_NAME ": Failed\n"); + return ret; +} + +/******* for bb_miiphy *******/ +static int sh_eth_bb_init(struct bb_miiphy_bus *bus) +{ return 0; } -int eth_init(bd_t *bd) +static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) { - int rc; - /* Allocate main device information structure */ - if (!(dev = malloc(sizeof(*dev)))) { - printf("eth_init: malloc failed\n"); - return -ENOMEM; - } + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; - memset(dev, 0, sizeof(*dev)); + outl(inl(PIR(port)) | PIR_MMD, PIR(port)); - dev->port = CONFIG_SH_ETHER_USE_PORT; - dev->port_info[dev->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + return 0; +} - sh_eth_get_mac(bd); +static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; - if ((rc = sh_eth_reset(dev)) || (rc = sh_eth_desc_init(dev))) - goto err; + outl(inl(PIR(port)) & ~PIR_MMD, PIR(port)); - if ((rc = sh_eth_config(dev, bd)) || (rc = sh_eth_start(dev))) - goto err_desc; + return 0; +} + +static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + if (v) + outl(inl(PIR(port)) | PIR_MDO, PIR(port)); + else + outl(inl(PIR(port)) & ~PIR_MDO, PIR(port)); return 0; +} -err_desc: - sh_eth_desc_free(dev); -err: - free(dev); - printf("eth_init: Failed\n"); - return rc; +static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + *v = (inl(PIR(port)) & PIR_MDI) >> 3; + + return 0; } + +static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + if (v) + outl(inl(PIR(port)) | PIR_MDC, PIR(port)); + else + outl(inl(PIR(port)) & ~PIR_MDC, PIR(port)); + + return 0; +} + +static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "sh_eth", + .init = sh_eth_bb_init, + .mdio_active = sh_eth_bb_mdio_active, + .mdio_tristate = sh_eth_bb_mdio_tristate, + .set_mdio = sh_eth_bb_set_mdio, + .get_mdio = sh_eth_bb_get_mdio, + .set_mdc = sh_eth_bb_set_mdc, + .delay = sh_eth_bb_delay, + } +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);