X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fconfigs%2FIDS8247.h;h=590abc30dfc379f0d3f511204f16ccd53606adca;hp=fbcbddb408de636ac82cfd69441698d0ceed8e33;hb=230187ce266889ad465b39ded6717805379e7ffe;hpb=5df70e91c72dab45b7d81e4568b12e5a5b5f90ec diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index fbcbddb408..590abc30df 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -2,23 +2,7 @@ * (C) Copyright 2005 * Heiko Schocher, DENX Software Engineering, * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -39,6 +23,8 @@ #define CPU_ID_STR "MPC8247" #define CONFIG_CPM2 1 /* Has a CPM2 */ +#define CONFIG_SYS_TEXT_BASE 0xfff00000 + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOUNT_LIMIT @@ -71,11 +57,10 @@ #define CONFIG_MISC_INIT_R 1 /* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SOFT_SPEED 400000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F /* * Software (bit-bang) I2C driver configuration */ @@ -125,8 +110,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" @@ -154,8 +137,8 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) +# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) # define CONFIG_SYS_CPMFCR_RAMTYPE 0 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) @@ -215,8 +198,6 @@ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ /* @@ -229,9 +210,9 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ /* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk + * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk * The main FLASH is whichever is connected to *CS0. */ #define CONFIG_SYS_FLASH0_BASE 0xFFF00000 @@ -244,7 +225,6 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ @@ -262,63 +242,8 @@ */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_LEGACY #define CONFIG_SYS_NAND0_BASE 0xE1000000 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define NAND_DISABLE_CE(nand) do \ -{ \ - *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \ -} while(0) - -#define NAND_ENABLE_CE(nand) do \ -{ \ - *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_SETALE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x9) = 0; \ -} while(0) - -#define NAND_CTL_CLRCLE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_SETCLE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0xa) = 0; \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) #endif /* CONFIG_CMD_NAND */ @@ -349,9 +274,8 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -363,19 +287,10 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - /*----------------------------------------------------------------------- * Cache Configuration */