X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fconfigs%2Fkorat.h;h=5494a6007dfb32c8903b388520d4a4d3456ade11;hp=d56da144879b9fdf8999924c66dc285df5b45143;hb=17998eff9021b7b579c0387e934d8c52603fe247;hpb=e0b0ec843085f96f4fe0738424835ee90e58bc00 diff --git a/include/configs/korat.h b/include/configs/korat.h index d56da14487..5494a6007d 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006-2007 @@ -9,20 +9,7 @@ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -35,9 +22,14 @@ * High Level Configuration Options */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 +#ifdef CONFIG_KORAT_PERMANENT +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#else +#define CONFIG_SYS_TEXT_BASE 0xF7F60000 +#endif + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -64,14 +56,12 @@ #define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000 #define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE) #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ - -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000) #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 @@ -84,19 +74,20 @@ /* 440EPx has 16KB of internal SRAM, so no need for D-Cache */ #undef CONFIG_SYS_INIT_RAM_DCACHE #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -138,23 +129,23 @@ /* * DDR SDRAM */ -#define CONFIG_SYS_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */ + /* per 440EPx Errata CHIP_11 */ /* * I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) @@ -173,42 +164,59 @@ #define CONFIG_SYS_DTT_MIN_TEMP -30 #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \ "echo" #undef CONFIG_BOOTARGS /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME korat -#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/korat/uImage\0" -#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_SYS_BOOTFILE \ - CONFIG_SYS_ROOTPATH \ + "u_boot=korat/u-boot.bin\0" \ + "load=tftp 200000 ${u_boot}\0" \ + "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \ + "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \ + "F7F60000 F7FBFFFF\0" \ + "upd=run load update\0" \ + "bootfile=korat/uImage\0" \ + "dtb=korat/korat.dtb\0" \ + "kernel_addr=F4000000\0" \ + "ramdisk_addr=F4400000\0" \ + "dtb_addr=F41E0000\0" \ + "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \ + "cp.b ${fileaddr} F4000000 ${filesize}\0" \ + "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \ + "cp.b ${fileaddr} F41E0000 ${filesize}\0" \ + "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \ + "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \ + "${dtb}\0" \ + "rd_size=73728\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "ramdisk_size=${rd_size}\0" \ + "usbdev=sda1\0" \ + "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "pciclk=33\0" \ + "addide=setenv bootargs ${bootargs} ide=reverse " \ + "idebus=${pciclk}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "kernel_addr=F4000000\0" \ - "ramdisk_addr=F4400000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load update\0" \ + "flash_cf=run usbargs addide addip addtty; " \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "flash_nfs=run nfsargs addide addip addtty; " \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "flash_self=run ramargs addip addtty; " \ + "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTCOMMAND "run flash_cf" #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -227,7 +235,6 @@ #define CONFIG_HAS_ETH0 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */ /* buffers & descriptors */ -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 3 @@ -266,7 +273,6 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C -#define CONFIG_I2C_CMD_TREE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -278,18 +284,17 @@ #define CONFIG_CMD_USB /* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ CONFIG_SYS_POST_UART) -#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */ @@ -301,7 +306,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -318,8 +322,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ @@ -336,6 +338,7 @@ */ /* General PCI */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -344,6 +347,7 @@ /* Board-specific PCI */ #define CONFIG_SYS_PCI_TARGET_INIT #define CONFIG_SYS_PCI_MASTER_INIT +#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ @@ -403,7 +407,7 @@ * GPIO10 Alt1 O x PerCS5 to expansion bus connector * GPIO11 Alt1 I x PerErr * GPIO12 GPIO O 0 ATMega !Reset - * GPIO13 GPIO O 1 SPI Atmega !SS + * GPIO13 GPIO x x Test Point 2 (TP2) * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) * GPIO15 GPIO O 0 CPU Run LED !On * GPIO16 Alt1 O x GMC1TxD0 @@ -478,7 +482,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ @@ -535,17 +539,8 @@ } \ } -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* Pass open firmware flat tree */