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(parent: 119a55f) | patch
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
authorYork Sun <yorksun@freescale.com>
Wed, 29 Feb 2012 12:36:51 +0000 (12:36 +0000)
committerAndy Fleming <afleming@freescale.com>
Wed, 25 Apr 2012 04:58:30 +0000 (23:58 -0500)
commit1ba62f10172ead798a8176435cfffff2f79f21c5
tree5e9b575825060fae4ebefa3193ad5f1124c0fefdtree | snapshot
parent119a55f9cff4884a0ad3353d8752ee8787e232dacommit | diff
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards

P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/freescale/p1010rdb/ddr.c diff | blob | history
board/freescale/p1_p2_rdb_pc/ddr.c diff | blob | history
include/configs/P1010RDB.h diff | blob | history
include/configs/p1_p2_rdb_pc.h diff | blob | history
UBoot for KaRo TX COM modules