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ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
authorKumar Gala <galak@kernel.crashing.org>
Fri, 13 Nov 2009 15:04:19 +0000 (09:04 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:49:08 +0000 (13:49 -0600)
commit355f4f85e90ce2e6d91883012c2993be7970c8b1
tree7380c8c9cd3d6464f0da09767b7fcd3ccf41c06atree | snapshot
parent94e9411b9dda182dd63d53ba6ea640c98b35db5fcommit | diff
ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation

Now that we track which TLB CAM entries are used we can allocate
entries on the fly.  Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc85xx/tlb.c diff | blob | history
UBoot for KaRo TX COM modules