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powerpc/mpc85xx: Add workaround for DDR erratum A004934
authorYork Sun <yorksun@freescale.com>
Mon, 8 Oct 2012 07:44:26 +0000 (07:44 +0000)
committerAndy Fleming <afleming@freescale.com>
Mon, 22 Oct 2012 19:31:29 +0000 (14:31 -0500)
commita1d558a20f1eaeae9927abc4e0978725d33bae53
tree3af577ebb7be24efd3c23d7a8559512d2f9bfa70tree | snapshot
parenteb5394120643922626f18e5fe7b0b3dc0ed43b9acommit | diff
powerpc/mpc85xx: Add workaround for DDR erratum A004934

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/cmd_errata.c diff | blob | history
arch/powerpc/cpu/mpc85xx/ddr-gen3.c diff | blob | history
arch/powerpc/include/asm/config_mpc85xx.h diff | blob | history
UBoot for KaRo TX COM modules