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imx: mx6q DDR3 init: Fix SDE_to_RST
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Wed, 30 Jan 2013 11:19:15 +0000 (11:19 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Feb 2013 12:52:30 +0000 (13:52 +0100)
commitada02b84636242f5142f74016dbedb50889e93d0
tree4468b2a516e6337b5fe0fc80ab53a1a3eeb4dcd8tree | snapshot
parentaa53149e1108ab9395ee8309ce6f90480bfdf34bcommit | diff
imx: mx6q DDR3 init: Fix SDE_to_RST

MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff | blob | history
UBoot for KaRo TX COM modules