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powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
authorShaohui Xie <Shaohui.Xie@freescale.com>
Tue, 13 Sep 2011 09:51:39 +0000 (17:51 +0800)
committerKumar Gala <galak@kernel.crashing.org>
Mon, 3 Oct 2011 13:29:54 +0000 (08:29 -0500)
commitba50fee6ae7e626bb2eda9d28403d7d3950f407a
tree7a6bd82233c3f92e547ba4a0e87170c57ffaa908tree | snapshot
parentd4b9106609a67617d8cef3bb6bce124974865388commit | diff
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0

CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/freescale/p2041rdb/cpld.c diff | blob | history
board/freescale/p2041rdb/cpld.h diff | blob | history
UBoot for KaRo TX COM modules