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(parent: 1c9aa76) | patch
Make DDR interleaving mode work correctly
authorHaiying Wang <Haiying.Wang@freescale.com>
Fri, 3 Oct 2008 16:36:39 +0000 (12:36 -0400)
committerWolfgang Denk <wd@denx.de>
Sat, 18 Oct 2008 19:54:04 +0000 (21:54 +0200)
commitdbbbb3abeff325855cae76e33d69d5665631443f
tree2df59a7ac7364e4c501e228c74db3cd5f14ad3b1tree | snapshot
parent1c9aa76bf9013069e24258f46f4687c9f98a02d6commit | diff
Make DDR interleaving mode work correctly

Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
cpu/mpc8xxx/ddr/main.c diff | blob | history
include/asm-ppc/fsl_ddr_sdram.h diff | blob | history
UBoot for KaRo TX COM modules