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(parent: 378bd1f) | patch
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
authorSricharan R <r.sricharan@ti.com>
Thu, 30 May 2013 03:19:34 +0000 (03:19 +0000)
committerTom Rini <trini@ti.com>
Mon, 10 Jun 2013 12:43:10 +0000 (08:43 -0400)
commitf9b814a8e99390d19628bc1b67c9567fc485d918
tree791ab819ecdd0bcb956b12a6004a0d5b63aa2601tree | snapshot
parent378bd1fb4e965a10b396140e964740c76c960c70commit | diff
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap-common/timer.c diff | blob | history
arch/arm/include/asm/arch-omap4/clock.h diff | blob | history
arch/arm/include/asm/arch-omap5/clock.h diff | blob | history
include/configs/omap4_common.h diff | blob | history
include/configs/omap5_common.h diff | blob | history
UBoot for KaRo TX COM modules