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powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
authorYork Sun <yorksun@freescale.com>
Mon, 8 Oct 2012 07:44:30 +0000 (07:44 +0000)
committerAndy Fleming <afleming@freescale.com>
Mon, 22 Oct 2012 19:31:32 +0000 (14:31 -0500)
commitffd06e0231ac3fd0c5810f39f6e23527948df1c7
tree7d648c2c312b9cc7a75c0350101aacc67afca399tree | snapshot
parent3f0997b3255c1498ac92453aa3a7a1cc95914dfdcommit | diff
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
README diff | blob | history
arch/powerpc/cpu/mpc85xx/fdt.c diff | blob | history
arch/powerpc/cpu/mpc85xx/mp.c diff | blob | history
arch/powerpc/cpu/mpc85xx/mp.h diff | blob | history
arch/powerpc/cpu/mpc85xx/release.S diff | blob | history
arch/powerpc/cpu/mpc85xx/tlb.c diff | blob | history
arch/powerpc/include/asm/config_mpc85xx.h diff | blob | history
doc/README.mpc85xx-spin-table [new file with mode: 0644] blob
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