Andreas Bießmann <andreas.devel@googlemail.com>
grasshopper AT32AP7000
+ atngw100mkii AT32AP7000
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return s5p_sdhci_init(base, 52000000, 400000, index);
+ return s5p_sdhci_init(base, index, bus_width);
}
#endif
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return s5p_sdhci_init(base, 52000000, 400000, index);
+ return s5p_sdhci_init(base, index, bus_width);
}
#endif
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+CONFIG_ARCH_DEVICE_TREE := microblaze
#undef DEBUG_INT
-extern void microblaze_disable_interrupts (void);
-extern void microblaze_enable_interrupts (void);
-
-void enable_interrupts (void)
+void enable_interrupts(void)
{
MSRSET(0x2);
}
-int disable_interrupts (void)
+int disable_interrupts(void)
{
unsigned int msr;
/* default handler */
static void def_hdlr(void)
{
- puts ("def_hdlr\n");
+ puts("def_hdlr\n");
}
static void enable_one_interrupt(int irq)
{
int mask;
int offset = 1;
+
offset <<= irq;
mask = intc->ier;
intc->ier = (mask | offset);
#ifdef DEBUG_INT
- printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+ printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
intc->ier);
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
{
int mask;
int offset = 1;
+
offset <<= irq;
mask = intc->ier;
intc->ier = (mask & ~offset);
#ifdef DEBUG_INT
- printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+ printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
intc->ier);
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
-/* adding new handler for interrupt */
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
{
struct irq_action *act;
+
/* irq out of range */
if ((irq < 0) || (irq > irq_no)) {
- puts ("IRQ out of range\n");
- return;
+ puts("IRQ out of range\n");
+ return -1;
}
act = &vecs[irq];
if (hdlr) { /* enable */
act->arg = arg;
act->count = 0;
enable_one_interrupt (irq);
- } else { /* disable */
- act->handler = (interrupt_handler_t *) def_hdlr;
- act->arg = (void *)irq;
- disable_one_interrupt (irq);
+ return 0;
}
+
+ /* Disable */
+ act->handler = (interrupt_handler_t *) def_hdlr;
+ act->arg = (void *)irq;
+ disable_one_interrupt(irq);
+ return 1;
}
/* initialization interrupt controller - hardware */
/* XIntc_Start - hw_interrupt enable and all interrupt enable */
intc->mer = 0x3;
#ifdef DEBUG_INT
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
return 0;
}
-void interrupt_handler (void)
+void interrupt_handler(void)
{
int irqs = intc->ivr; /* find active interrupt */
int mask = 1;
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
- brai board_init
+ brai board_init_f
1: bri 1b
/*
#include <asm/microblaze_intc.h>
volatile int timestamp = 0;
+microblaze_timer_t *tmr;
-#ifdef CONFIG_SYS_TIMER_0
ulong get_timer (ulong base)
{
- return (timestamp - base);
+ if (tmr)
+ return timestamp - base;
+ return timestamp++ - base;
}
-#else
-ulong get_timer (ulong base)
-{
- return (timestamp++ - base);
-}
-#endif
-#ifdef CONFIG_SYS_TIMER_0
void __udelay(unsigned long usec)
{
- int i;
+ u32 i;
- i = get_timer(0);
- while ((get_timer(0) - i) < (usec / 1000))
- ;
+ if (tmr) {
+ i = get_timer(0);
+ while ((get_timer(0) - i) < (usec / 1000))
+ ;
+ } else {
+ for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
+ ;
+ }
}
-#else
-void __udelay(unsigned long usec)
-{
- unsigned int i;
- for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++)
- ;
-}
-#endif
-
-#ifdef CONFIG_SYS_TIMER_0
-microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
-
-void timer_isr (void *arg)
+static void timer_isr(void *arg)
{
timestamp++;
tmr->control = tmr->control | TIMER_INTERRUPT;
int timer_init (void)
{
- tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
- tmr->control = TIMER_INTERRUPT | TIMER_RESET;
- tmr->control =
- TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
- timestamp = 0;
- install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+ int irq = -1;
+ u32 preload = 0;
+ u32 ret = 0;
+
+#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
+ preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
+ irq = CONFIG_SYS_TIMER_0_IRQ;
+ tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
+#endif
+
+ if (tmr && preload && irq >= 0) {
+ tmr->loadreg = preload;
+ tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+ tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
+ TIMER_RELOAD | TIMER_DOWN_COUNT;
+ timestamp = 0;
+ ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
+ if (ret)
+ tmr = NULL;
+ }
+
+ /* No problem if timer is not found/initialized */
return 0;
}
-#endif
/*
* This function is derived from PowerPC code (read timebase as long long).
.data ALIGN(0x4):
{
__data_start = .;
+ dts/libdts.o (.data)
*(.data)
__data_end = .;
}
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#endif
unsigned long env_addr; /* Address of Environment struct */
+ const void *fdt_blob; /* Our device tree, NULL if none */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
void **jt; /* jump table */
int count; /* number of interrupt */
};
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+/**
+ * Register and unregister interrupt handler rutines
+ *
+ * @param irq IRQ number
+ * @param hdlr Interrupt handler rutine
+ * @param arg Pointer to argument which is passed to int. handler rutine
+ * @return 0 if registration pass, 1 if unregistration pass,
+ * or an error code < 0 otherwise
+ */
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
void *arg);
int interrupts_init(void);
int loadreg; /* load register TLR */
int counter; /* timer/counter register */
} microblaze_timer_t;
+
+int timer_init(void);
+
extern char __end[];
extern char __text_start[];
+/* Microblaze board initialization function */
+void board_init(void);
+
#endif /* __ASM_MICROBLAZE_PROCESSOR_H */
#include <stdio_dev.h>
#include <serial.h>
#include <net.h>
+#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
+#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SYS_GPIO_0
-extern int gpio_init (void);
-#endif
-#ifdef CONFIG_SYS_TIMER_0
-extern int timer_init (void);
-#endif
-#ifdef CONFIG_SYS_FSL_2
-extern void fsl_init2 (void);
-#endif
-
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
init_fnc_t *init_sequence[] = {
env_init,
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_check_fdt,
+#endif
serial_init,
console_init_f,
-#ifdef CONFIG_SYS_GPIO_0
- gpio_init,
-#endif
interrupts_init,
-#ifdef CONFIG_SYS_TIMER_0
timer_init,
-#endif
-#ifdef CONFIG_SYS_FSL_2
- fsl_init2,
-#endif
NULL,
};
unsigned long monitor_flash_len;
-void board_init (void)
+void board_init_f(ulong not_used)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
- GENERATED_BD_INFO_SIZE);
- char *s;
+ __maybe_unused char *s;
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
#endif
monitor_flash_len = __end - __text_start;
+#ifdef CONFIG_OF_EMBED
+ /* Get a pointer to the FDT */
+ gd->fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+ /* FDT is at end of image */
+ gd->fdt_blob = (void *)__end;
+#endif
+ /* Allow the early environment to override the fdt address */
+ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+ (uintptr_t)gd->fdt_blob);
+
/*
* The Malloc area is immediately below the monitor copy in DRAM
* aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
}
}
+#ifdef CONFIG_OF_CONTROL
+ /* For now, put this check after the console is ready */
+ if (fdtdec_prepare_fdt()) {
+ panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+ "doc/README.fdt-control");
+ } else
+ printf("DTB: 0x%x\n", (u32)gd->fdt_blob);
+#endif
+
puts ("SDRAM :\n");
printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
#if defined(CONFIG_CMD_FLASH)
puts ("Flash: ");
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- if (0 < (flash_size = flash_init ())) {
- bd->bi_flashsize = flash_size;
- bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size;
+ flash_size = flash_init();
+ if (bd->bi_flashstart && flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size (flash_size, "");
/*
s = getenv ("flashchecksum");
if (s && (*s == 'y')) {
printf (" CRC: %08X",
- crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
+ crc32(0, (const u8 *)bd->bi_flashstart,
+ flash_size)
);
}
putc ('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size (flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
+ bd->bi_flashsize = flash_size;
+ bd->bi_flashoffset = bd->bi_flashstart + flash_size;
} else {
puts ("Flash init FAILED");
bd->bi_flashstart = 0;
/* Initialize the console (after the relocation and devices init) */
console_init_r();
+ board_init();
+
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
CROSS_COMPILE ?= mips_4KC-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+# Handle special prefix in ELDK 4.0 toolchain
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ENDIANNESS := -EB
+endif
+
+# Default to EB if no endianess is configured
+ENDIANNESS ?= -EB
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
PLATFORM_CPPFLAGS += -msoft-float
-PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections
#
MIPSFLAGS := -march=mips32r2
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
-endif
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
-endif
-
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS)
-PLATFORM_LDFLAGS += $(ENDIANNESS)
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
# MA 02111-1307 USA
#
-PLATFORM_CPPFLAGS += -march=mips32 -EL
-PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -march=mips32
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
writew(100, &wdt->tdr); /* wdt_set_data(100) */
writew(0, &wdt->tcnt); /* wdt_set_count(0); */
- writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
+ writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
while (1)
void reset_timer_masked(void)
{
/* reset time */
- gd->lastinc = readw(&tcu->tcnt0);
+ gd->lastinc = readl(&tcu->tcnt0);
gd->tbl = 0;
}
ulong get_timer_masked(void)
{
- ulong now = readw(&tcu->tcnt0);
+ ulong now = readl(&tcu->tcnt0);
if (gd->lastinc <= now)
gd->tbl += now - gd->lastinc; /* normal mode */
int timer_init(void)
{
- writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
+ writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
- writew(0, &tcu->tcnt0);
- writew(0, &tcu->tdhr0);
- writew(TIMER_FDATA, &tcu->tdfr0);
+ writel(0, &tcu->tcnt0);
+ writel(0, &tcu->tdhr0);
+ writel(TIMER_FDATA, &tcu->tdfr0);
/* mask irqs */
writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
LIB = $(obj)lib$(ARCH).o
+## Build a couple of necessary functions into a private libgcc
+LIBGCC = $(obj)libgcc.o
+GLSOBJS += ashldi3.o
+GLSOBJS += ashrdi3.o
+GLSOBJS += lshrdi3.o
+LGOBJS := $(addprefix $(obj),$(GLSOBJS))
+
SOBJS-y +=
COBJS-y += board.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+# Always build libmips.o
+TARGETS := $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS += $(LIBGCC)
+endif
+
+all: $(TARGETS)
+
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(LIBGCC): $(obj).depend $(LGOBJS)
+ $(call cmd_link_o_target, $(LGOBJS))
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ w.s.low = 0;
+ w.s.high = (unsigned int) uu.s.low << -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+ w.s.low = (unsigned int) uu.s.low << b;
+ w.s.high = ((unsigned int) uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high =
+ uu.s.high >> 31;
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+ int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+ int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+ struct DWstruct s;
+ long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */
--- /dev/null
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ w.s.high = 0;
+ w.s.low = (unsigned int) uu.s.high >> -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+ w.s.high = (unsigned int) uu.s.high >> b;
+ w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <spi.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
+ .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 10,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 6,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
+ | HMATRIX_BIT(EBI_NAND_ENABLE));
+
+ portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
+ PORTMUX_DRIVE_HIGH);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
+ | PORTMUX_DRIVE_MIN);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
static void cpm_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- uint32_t reg = readw(&cpm->clkgr);
+ uint32_t reg = readl(&cpm->clkgr);
reg |= CPM_CLKGR_IPU |
CPM_CLKGR_CIM |
CPM_CLKGR_UDC |
CPM_CLKGR_AIC1;
- writew(reg, &cpm->clkgr);
+ writel(reg, &cpm->clkgr);
}
int board_early_init_f(void)
#include <common.h>
#include <config.h>
#include <netdev.h>
+#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
}
#endif
+void board_init(void)
+{
+ gpio_init();
+#ifdef CONFIG_SYS_FSL_2
+ fsl_init2();
+#endif
+}
+
int board_eth_init(bd_t *bis)
{
int ret = 0;
paz00 arm armv7:arm720t paz00 compal tegra20
trimslice arm armv7:arm720t trimslice compulab tegra20
atngw100 avr32 at32ap - atmel at32ap700x
+atngw100mkii avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64
M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
-qemu_mips mips mips32 qemu-mips - - qemu-mips
+qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
+qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
}
}
+ return CMD_RET_SUCCESS;
+ }
+
+ if (!working_fdt) {
+ puts(
+ "No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n"
+ "Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
/*
* Move the working_fdt
*/
- } else if (strncmp(argv[1], "mo", 2) == 0) {
+ if (strncmp(argv[1], "mo", 2) == 0) {
struct fdt_header *newaddr;
int len;
int err;
U_BOOT_CMD(
mmcinfo, 1, 0, do_mmcinfo,
"display MMC info",
- " - device number of the device to dislay info of\n"
- ""
+ "- dislay info of the current MMC device"
);
int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_NEEDS_MANUAL_RELOC
void malloc_bin_reloc (void)
{
- unsigned long *p = (unsigned long *)(&av_[2]);
- int i;
- for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) {
- *p++ += gd->reloc_off;
- }
+ mbinptr *p = &av_[2];
+ size_t i;
+
+ for (i = 2; i < ARRAY_SIZE(av_); ++i, ++p)
+ *p = (mbinptr)((ulong)*p + gd->reloc_off);
}
#endif
return -1;
}
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) {
+ if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ CONFIG_SYS_MMC_ENV_PART)) {
+ puts("MMC partition switch failed\n");
+ return -1;
+ }
+ }
+#endif
+
return 0;
}
+static void fini_mmc_for_env(struct mmc *mmc)
+{
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num)
+ mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ mmc->part_num);
+#endif
+}
+
#ifdef CONFIG_CMD_SAVEENV
static inline int write_env(struct mmc *mmc, unsigned long size,
unsigned long offset, const void *buffer)
char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
+ if (init_mmc_for_env(mmc))
return 1;
+ if (mmc_get_env_addr(mmc, &offset)) {
+ ret = 1;
+ goto fini;
+ }
+
res = (char *)&env_new->data;
len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
- return 1;
+ ret = 1;
+ goto fini;
}
env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE);
printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts("failed\n");
- return 1;
+ ret = 1;
+ goto fini;
}
puts("done\n");
- return 0;
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+ return ret;
}
#endif /* CONFIG_CMD_SAVEENV */
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
- return set_default_env(NULL);
+ if (init_mmc_for_env(mmc)) {
+ ret = 1;
+ goto err;
+ }
- if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf))
- return set_default_env(NULL);
+ if (mmc_get_env_addr(mmc, &offset)) {
+ ret = 1;
+ goto fini;
+ }
+
+ if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) {
+ ret = 1;
+ goto fini;
+ }
env_import(buf, 1);
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+err:
+ if (ret)
+ set_default_env(NULL);
#endif
}
* to be the base address for the chip, usually in the local
* peripheral bus.
*/
-#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8)
+
+static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
+static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
+
+static void ace_writew(u16 val, unsigned off)
+{
+ if (width == 8) {
#if !defined(__BIG_ENDIAN)
-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \
- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)))
-#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \
- writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
+ writeb(val >> 8, base + off);
+ writeb(val, base + off + 1);
#else
-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \
- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8))
-#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \
- writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
+ writeb(val, base + off);
+ writeb(val >> 8, base + off + 1);
#endif
+ }
+ out16(base + off, val);
+}
+
+static u16 ace_readw(unsigned off)
+{
+ if (width == 8) {
+#if !defined(__BIG_ENDIAN)
+ return (readb(base + off) << 8) | readb(base + off + 1);
#else
-#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off))
-#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val))
+ return readb(base + off) | (readb(base + off + 1) << 8);
#endif
+ }
-/* */
+ return in16(base + off);
+}
static unsigned long systemace_read(int dev, unsigned long start,
unsigned long blkcnt, void *buffer);
/*
* Ensure the correct bus mode (8/16 bits) gets enabled
*/
- ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
+ ace_writew(width == 8 ? 0 : 0x0001, 0);
init_part(&systemace_dev);
debug("CMD%d time out\n", cmd->cmdidx);
return TIMEOUT;
} else if ((hoststatus & SDI_STA_CCRCFAIL) &&
- (cmd->flags & MMC_RSP_CRC)) {
+ (cmd->resp_type & MMC_RSP_CRC)) {
printf("CMD%d CRC error\n", cmd->cmdidx);
return -EILSEQ;
}
status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
printf("CURR STATE:%d\n", status);
#endif
- if (!timeout) {
+ if (timeout <= 0) {
printf("Timeout waiting card ready\n");
return TIMEOUT;
}
}
-int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
+int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
- data.dest = ext_csd;
+ data.dest = (char *)ext_csd;
data.blocks = 1;
data.blocksize = 512;
data.flags = MMC_DATA_READ;
int mmc_change_freq(struct mmc *mmc)
{
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
char cardtype;
int err;
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
- ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512);
int timeout = 1000;
#ifdef CONFIG_MMC_SPI_CRC_ON
}
/* store the partition info of emmc */
- if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT)
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+ ext_csd[EXT_CSD_BOOT_MULT])
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
}
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28,
(mmc->cid[2] >> 24) & 0xf);
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
init_part(&mmc->block_dev);
+#endif
return 0;
}
block_dev_desc_t *mmc_get_dev(int dev)
{
struct mmc *mmc = find_mmc_device(dev);
- if (!mmc)
+ if (!mmc || mmc_init(mmc))
return NULL;
- mmc_init(mmc);
return &mmc->block_dev;
}
#endif
int ret;
/* The card can send a "busy" response */
- if (cmd->flags & MMC_RSP_BUSY)
+ if (cmd->resp_type & MMC_RSP_BUSY)
cmdat |= MMC_CMDAT_BUSY;
/* Inform the controller about response type */
/* The command response didn't arrive */
if (stat & MMC_STAT_TIME_OUT_RESPONSE)
return -ETIMEDOUT;
- else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) {
+ else if (stat & MMC_STAT_RES_CRC_ERROR
+ && cmd->resp_type & MMC_RSP_CRC) {
#ifdef PXAMMC_CRC_SKIP
- if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31))
+ if (cmd->resp_type & MMC_RSP_136
+ && cmd->response[0] & (1 << 31))
printf("Ignoring CRC, this may be dangerous!\n");
else
#endif
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/clk.h>
static char *S5P_NAME = "SAMSUNG SDHCI";
static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
* 00 = Delay3 (inverter delay)
* 10 = Delay4 (inverter delay + 2ns)
*/
- val = SDHCI_CTRL3_FCSEL3 | SDHCI_CTRL3_FCSEL1;
+ val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
sdhci_writel(host, val, SDHCI_CONTROL3);
/*
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
{
struct sdhci_host *host = NULL;
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
host->name = S5P_NAME;
host->ioaddr = (void *)regbase;
- host->quirks = quirks;
- host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE;
+ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- if (quirks & SDHCI_QUIRK_REG32_RW)
- host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
- else
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->set_control_reg = &s5p_sdhci_set_control_reg;
+ host->set_clock = set_mmc_clk;
+ host->index = index;
host->host_caps = MMC_MODE_HC;
- add_sdhci(host, max_clk, min_clk);
+ add_sdhci(host, 52000000, 400000);
return 0;
}
if (clock == 0)
return 0;
- if (host->version >= SDHCI_SPEC_300) {
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
if (mmc->f_max <= clock)
div = 1;
}
div >>= 1;
+ if (host->set_clock)
+ host->set_clock(host->index, div);
+
clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
}
}
+ sdhci_set_power(host, fls(mmc->voltages) - 1);
+
+ if (host->quirks & SDHCI_QUIRK_NO_CD) {
+ unsigned int status;
+
+ sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
+ SDHCI_HOST_CONTROL);
+
+ status = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ while ((!(status & SDHCI_CARD_PRESENT)) ||
+ (!(status & SDHCI_CARD_STATE_STABLE)) ||
+ (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
+ status = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ }
+
/* Eable all state */
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
- sdhci_set_power(host, fls(mmc->voltages) - 1);
-
return 0;
}
if (max_clk)
mmc->f_max = max_clk;
else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
if (min_clk)
mmc->f_min = min_clk;
else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
else
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
mmc->f_max = CLKDEV_EMMC_DATA;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
- MMC_MODE_8BIT;
+ MMC_MODE_8BIT | MMC_MODE_HC;
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
mmc->send_cmd = sh_mmcif_request;
mmc->set_ios = sh_mmcif_set_ios;
return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA;
}
+static int uartlite_serial_init(const int port)
+{
+ if (userial_ports[port])
+ return 0;
+ return -1;
+}
+
#if !defined(CONFIG_SERIAL_MULTI)
int serial_init(void)
{
- /* FIXME: Nothing for now. We should initialize fifo, etc */
- return 0;
+ return uartlite_serial_init(0);
}
void serial_setbrg(void)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int userial##port##_init(void) \
- { return(0); } \
+ { return uartlite_serial_init(port); } \
void userial##port##_setbrg(void) {} \
int userial##port##_getc(void) \
{ return uartlite_serial_getc(port); } \
__weak struct serial_device *default_serial_console(void)
{
-# ifdef XILINX_UARTLITE_BASEADDR
- return &uartlite_serial0_device;
-# endif /* XILINX_UARTLITE_BASEADDR */
-# ifdef XILINX_UARTLITE_BASEADDR1
- return &uartlite_serial1_device;
-# endif /* XILINX_UARTLITE_BASEADDR1 */
-# ifdef XILINX_UARTLITE_BASEADDR2
- return &uartlite_serial2_device;
-# endif /* XILINX_UARTLITE_BASEADDR2 */
-# ifdef XILINX_UARTLITE_BASEADDR3
- return &uartlite_serial3_device;
-# endif /* XILINX_UARTLITE_BASEADDR3 */
+ if (userial_ports[0])
+ return &uartlite_serial0_device;
+ if (userial_ports[1])
+ return &uartlite_serial1_device;
+ if (userial_ports[2])
+ return &uartlite_serial2_device;
+ if (userial_ports[3])
+ return &uartlite_serial3_device;
+
+ return NULL;
}
#endif /* CONFIG_SERIAL_MULTI */
unsigned int max_hz, unsigned int mode)
{
struct xilinx_spi_slave *xilspi;
- struct xilinx_spi_reg *regs;
if (!spi_cs_is_valid(bus, cs)) {
printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
static int gzip_decompress(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len)
{
- unsigned long len = in_len;
- return zunzip(out, *out_len, (unsigned char *)in, &len, 0, 0);
+ return zunzip(out, *out_len, (unsigned char *)in,
+ (unsigned long *)out_len, 0, 0);
}
/* Fake description object for the "none" compressor */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AVR32
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATNGW100MKII
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ 20000000
+#define CONFIG_SYS_PLL0_DIV 1
+#define CONFIG_SYS_PLL0_MUL 7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB 1
+
+/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
+#define CONFIG_SYS_NR_VM_REGIONS 3
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT 0x04
+
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "root=mtd:main rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND \
+ "fsload 0x10400000 /uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS 5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
+#define CONFIG_ATMEL_SPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_SYS_DCACHE_LINESZ 32
+#define CONFIG_SYS_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_SIZE 0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 65536
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#endif /* __CONFIG_H */
#endif
/* timer */
-#ifdef XILINX_TIMER_BASEADDR
-# if (XILINX_TIMER_IRQ != -1)
-# define CONFIG_SYS_TIMER_0 1
+#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
-# define FREQUENCE XILINX_CLOCK_FREQ
-# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
-# endif
-#elif XILINX_CLOCK_FREQ
-# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
-#else
-# error BAD CLOCK FREQ
#endif
+
/* FSL */
/* #define CONFIG_SYS_FSL_2 */
/* #define FSL_INTR_2 1 */
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "qemu-mips # " /* Monitor Command Prompt */
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT "qemu-mipsel # "
+#else
+#define CONFIG_SYS_PROMPT "qemu-mips # "
+#endif
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define __CONFIG_QI_LB60_H
#define CONFIG_MIPS32 /* MIPS32 CPU core */
+#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_JZSOC /* Jz SoC */
#define CONFIG_JZ4740 /* Jz4740 SoC */
#define CONFIG_NAND_JZ4740
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_MMC
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
/* PWM */
#define CONFIG_PWM
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
* particular card is standard practice as far as I know.
*/
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
+#define EXT_CSD_BOOT_MULT 226 /* RO */
/*
* EXT_CSD field definitions
#define SDHCI_SPACE_AVAILABLE 0x00000400
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
+#define SDHCI_CARD_STATE_STABLE 0x00020000
+#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
#define SDHCI_WRITE_PROTECT 0x00080000
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
-#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CD_TEST_INS 0x40
+#define SDHCI_CTRL_CD_TEST 0x80
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
+#define SDHCI_QUIRK_NO_CD (1 << 5)
/* to make gcc happy */
struct sdhci_host;
unsigned int clock;
struct mmc *mmc;
const struct sdhci_ops *ops;
+ int index;
void (*set_control_reg)(struct sdhci_host *host);
+ void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
};
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT)
+ defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
+ defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
projects / karo-tx-uboot.git / commitdiff