# and Cc: the <u-boot@lists.denx.de> mailing list. #
# #
# Note: lists sorted by Maintainer Name #
+ # Note: These are the maintainers for specific *boards*. The #
+ # custodians for general architectures and subsystems can #
+ # be found here -- http://www.denx.de/wiki/U-Boot/Custodians #
+ # #
#########################################################################
Stefan Roese <sr@denx.de>
+ a3m071 MPC5200
+
P3M7448 MPC7448
uc100 MPC857
trizepsiv xscale/pxa
twister omap3
vision2 i.MX51
+ woodburn i.MX35
Lukasz Dalek <luk0104@gmail.com>
apx4devkit i.MX28
- Luka Perkov <uboot@lukaperkov.net>
+ Luka Perkov <luka@openwrt.org>
ib62x0 ARM926EJS
iconnect ARM926EJS
OBJS = $(CPUDIR)/start.o
ifeq ($(CPU),x86)
- OBJS += $(CPUDIR)/start16.o
- OBJS += $(CPUDIR)/resetvec.o
+ RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
+ RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
endif
ifeq ($(CPU),ppc4xx)
OBJS += $(CPUDIR)/resetvec.o
OBJS += $(CPUDIR)/resetvec.o
endif
- OBJS := $(addprefix $(obj),$(OBJS))
+ OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
LIBS-y += drivers/net/phy/libphy.o
LIBS-y += drivers/pci/libpci.o
LIBS-y += drivers/pcmcia/libpcmcia.o
- LIBS-y += drivers/power/libpower.o
+ LIBS-y += drivers/power/libpower.o \
+ drivers/power/fuel_gauge/libfuel_gauge.o \
+ drivers/power/pmic/libpmic.o \
+ drivers/power/battery/libbattery.o
LIBS-y += drivers/spi/libspi.o
LIBS-y += drivers/dfu/libdfu.o
ifeq ($(CPU),mpc83xx)
LIBS-y += drivers/usb/gadget/libusb_gadget.o
LIBS-y += drivers/usb/host/libusb_host.o
LIBS-y += drivers/usb/musb/libusb_musb.o
+ LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
LIBS-y += drivers/usb/phy/libusb_phy.o
LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
LIBS-y += drivers/video/libvideo.o
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
BOARD_SIZE_CHECK = \
@actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=$(CONFIG_BOARD_SIZE_LIMIT); \
+ limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:"; \
- echo " limit: $$limit bytes"; \
- echo " actual: $$actual bytes"; \
- echo " excess: $$((actual - limit)) bytes"; \
+ echo "$@ exceeds file size limit:" >&2 ; \
+ echo " limit: $$limit bytes" >&2 ; \
+ echo " actual: $$actual bytes" >&2 ; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
exit 1; \
fi
else
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
# enable combined SPL/u-boot/dtb rules for tegra
$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
+ #
+ # U-Boot entry point, needed for booting of full-blown U-Boot
+ # from the SPL U-Boot version.
+ #
+ ifndef CONFIG_SYS_UBOOT_START
+ CONFIG_SYS_UBOOT_START := 0
+ endif
+
$(obj)u-boot.img: $(obj)u-boot.bin
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+ -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_UBOOT_START) \
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
- $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
- $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
- rm $(obj)u-boot-ubl.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+ $(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
+ $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
+
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
-T aisimage \
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+ elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
rm $(obj)spl/u-boot-spl-pad.bin
endif
+ $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
+ cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
echo '*** Your board is configured for THUMB mode.'; \
false; \
fi
+
+ # GCC 3.x is reported to have problems generating the type of relocation
+ # that U-Boot wants.
+ # See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+ checkgcc4:
+ @if test $(call cc-version) -lt 0400; then \
+ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+ false; \
+ fi
+
#
# Auto-generate the autoconf.mk file (which is included by all makefiles)
#
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
- @$(MAKE) -C doc/DocBook/ cleandocs
+ @$(MAKE) -s -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
+ @rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
#include <asm/arch/mx35_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
- #include <pmic.h>
+ #include <power/pmic.h>
#include <fsl_pmic.h>
#include <mmc.h>
#include <fsl_esdhc.h>
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
+static void setup_iomux_usbotg(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
static void setup_iomux_fec(void)
{
int pad;
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
+ setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();
static inline int pmic_detect(void)
{
unsigned int id;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
pmic_reg_read(p, REG_IDENTIFICATION, &id);
u8 val;
u32 pmic_val;
struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
- pmic_init();
if (pmic_detect()) {
- p = get_pmic();
+ p = pmic_get("FSL_PMIC");
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
MUX_CONFIG_ALT1);
--- /dev/null
- #include <pmic.h>
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
- pmic_init();
- p = get_pmic();
++#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD 7
+#define GPIO_MMC_WP 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int woodburn_init(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_fec();
+
+ /* setup GPIO1_4 FEC_ENABLE signal */
+ mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+ gpio_direction_output(4, 1);
+ mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+ gpio_direction_output(9, 0);
+ gpio_set_value(9, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+ /* Set the stack pointer. */
+ asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+ /* Initialize MUX and SDRAM */
+ woodburn_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ timer_init();
+
+ board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+ return woodburn_init();
+}
+
+
+int board_init(void)
+{
+ struct pmic *p;
+ u32 val;
++ int ret;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
++ ret = pmic_init(I2C_PMIC);
++ if (ret)
++ return ret;
++
++ p = pmic_get("FSL_PMIC");
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ /* Set SWILIMB */
+ val |= (1 << 22);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VGEN1 to 3.15V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VGEN1_MASK);
+ val |= VGEN1_3_15;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN;
+ pmic_reg_write(p, REG_MODE_0, val);
+ udelay(2000);
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ /* configure pins for SDHC1 only */
+ mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+ /* MMC Card Detect on GPIO1_7 */
+ mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+ gpio_direction_input(GPIO_MMC_CD);
+
+ mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+ gpio_direction_output(GPIO_MMC_WP, 0);
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
+woodburn arm arm1136 - - mx35
+woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
+ at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
cobra5272 m68k mcf52x2 cobra5272 -
idmr m68k mcf52x2
- eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFFE00000
+ eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000
eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000
TASREG m68k mcf52x2 tasreg esd
M5208EVBE m68k mcf52x2 m5208evbe freescale
mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
cmi_mpc5xx powerpc mpc5xx cmi
PATI powerpc mpc5xx pati mpl
+ a3m071 powerpc mpc5xxx a3m071
a4m072 powerpc mpc5xxx a4m072
BC3450 powerpc mpc5xxx bc3450
canmb powerpc mpc5xxx
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+ P5040DS powerpc mpc85xx corenet_ds freescale
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
gr_ep2s60 sparc leon3 - gaisler
grsim sparc leon3 - gaisler
gr_xc3s_1500 sparc leon3 - gaisler
- coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
+ coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
# Target ARCH CPU Board name Vendor SoC Options
#include <common.h>
#include <spi.h>
- #include <pmic.h>
+ #include <power/pmic.h>
#include <fsl_pmic.h>
+ #include <errno.h>
- #if defined(CONFIG_PMIC_SPI)
+#if defined(CONFIG_PMIC_FSL_MC13892)
+#define FSL_PMIC_I2C_LENGTH 3
+#elif defined(CONFIG_PMIC_FSL_MC34704)
+#define FSL_PMIC_I2C_LENGTH 1
+#endif
+
+ #if defined(CONFIG_POWER_SPI)
static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
{
return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
}
#endif
- int pmic_init(void)
+ int pmic_init(unsigned char bus)
{
- struct pmic *p = get_pmic();
static const char name[] = "FSL_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
p->name = name;
p->number_of_regs = PMIC_NUM_OF_REGS;
- #if defined(CONFIG_PMIC_SPI)
+ #if defined(CONFIG_POWER_SPI)
p->interface = PMIC_SPI;
p->bus = CONFIG_FSL_PMIC_BUS;
p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN;
p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END;
p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
- #elif defined(CONFIG_PMIC_I2C)
+ #elif defined(CONFIG_POWER_I2C)
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
- p->hw.i2c.tx_num = 3;
+ p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
- p->bus = I2C_PMIC;
+ p->bus = bus;
#else
- #error "You must select CONFIG_PMIC_SPI or CONFIG_PMIC_I2C"
+ #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#endif
return 0;
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
/*
* PMIC Configs
*/
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT 0
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
+ MXC_EHCI_POWER_PINS_ENABLED | \
+ MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#endif
/* SPI PMIC */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
#define CONFIG_FSL_PMIC_CLK 25000000
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
#endif
#define CONFIG_MXC_SPI
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
***********************************************************/
#include <config_cmd_default.h>
-
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_DATE
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* FLASH and environment organization
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Configs */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_DIALOG_PMIC
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_DIALOG_POWER
+ #define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_PREBOOT ""
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
/* 166 MHz DDR RAM */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
--- /dev/null
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
- #define CONFIG_PMIC_FSL
++#define CONFIG_POWER
++#define CONFIG_POWER_I2C
++#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+#define CONFIG_RTC_MC13XXX
+
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
+ IRAM_BASE_ADDR - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
+ "32m(rootfb)," \
+ "64m(pcache)," \
+ "64m(app1)," \
+ "10m(app2),-(spool);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 7
+#endif
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME woodburn
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=80800000\0" \
+ "kernel_addr_r=80800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +80000;" \
+ "erase ${uboot_addr} +80000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
endif
START := $(START_PATH)/start.o
+ ifeq ($(CPU),x86)
+ START += $(START_PATH)/start16.o
+ START += $(START_PATH)/resetvec.o
+ endif
+ ifeq ($(CPU),ppc4xx)
+ START += $(START_PATH)/resetvec.o
+ endif
+ ifeq ($(CPU),mpc85xx)
+ START += $(START_PATH)/resetvec.o
+ endif
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+
LIBS-y += $(CPUDIR)/lib$(CPU).o
+ ifeq ($(CPU),mpc83xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+ ifeq ($(CPU),mpc85xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+ ifeq ($(CPU),mpc86xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+
ifdef SOC
LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
endif
$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+ifneq ($(CONFIG_IMX_CONFIG),)
+$(OBJTREE)/SPL: $(obj)u-boot-spl.bin
+ $(OBJTREE)/tools/mkimage -n $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
ALL-y += $(obj)u-boot-spl.bin
ifdef CONFIG_SAMSUNG
projects / karo-tx-uboot.git / commitdiff