/errlog
/reloc_off
-!/spl/Makefile
/spl/*
+!/spl/Makefile
/tpl/
#
#
VERSION = 2014
-PATCHLEVEL = 04
+PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
#
# If $(quiet) is empty, the whole command will be printed.
-# If it is set to "quiet_", only the short version will be printed.
+# If it is set to "quiet_", only the short version will be printed.
# If it is set to "silent_", nothing will be printed at all, since
# the variable $(silent_cmd_cc_o_c) doesn't exist.
#
endif
endif
+# Prohibit date/time macros, which would make the build non-deterministic
+KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
+
ifneq ($(CONFIG_SYS_TEXT_BASE),)
KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
$(call cmd,u-boot__) common/system_map.o
endif
-# The actual objects are generated when descending,
+# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
-# FIXME Should go into a make.lib or something
+# FIXME Should go into a make.lib or something
# ===========================================================================
quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))
directory according to the instructions in cogent/README.
+Sandbox Environment:
+--------------------
+
+U-Boot can be built natively to run on a Linux host using the 'sandbox'
+board. This allows feature development which is not board- or architecture-
+specific to be undertaken on a native platform. The sandbox is also used to
+run some of U-Boot's tests.
+
+See board/sandbox/sandbox/README.sandbox for more details.
+
+
Configuration Options:
----------------------
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
+ CONFIG_SYS_GENERIC_GLOBAL_DATA
+ Defines global data is initialized in generic board board_init_f().
+ If this macro is defined, global data is created and cleared in
+ generic board board_init_f(). Without this macro, architecture/board
+ should initialize global data before calling board_init_f().
+
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
+ CONFIG_SERIAL_HW_FLOW_CONTROL
+
+ Define this variable to enable hw flow control in serial driver.
+ Current user of this option is drivers/serial/nsl16550.c driver
- Console Interface:
Depending on board, define exactly one serial port
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#endif /*__ASM_ARC_CONFIG_H_ */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#ifndef __ASSEMBLY__
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
- gd->bd->bi_baudrate = gd->baudrate;
/* Ram ist board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
- unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;
*/
bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
bd->bi_dram[0].size = sdram_size;
- bd->bi_baudrate = gd->baudrate;
memcpy(new_gd, gd, sizeof(gd_t));
+++ /dev/null
-/*
- * net.h - misc Blackfin network helpers
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_RAND_MAC__
-#define __ASM_BFIN_RAND_MAC__
-
-/* If the board does not have a real MAC assigned to it, then generate a
- * locally administrated pseudo-random one based on CYCLES and compile date.
- */
-static inline void bfin_gen_rand_mac(uchar *mac_addr)
-{
- /* make something up */
- const char s[] = __DATE__;
- size_t i;
- u32 cycles;
- for (i = 0; i < 6; ++i) {
- asm("%0 = CYCLES;" : "=r" (cycles));
- mac_addr[i] = cycles ^ s[i];
- }
- mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
-}
-
-#endif
#define _U_BOOT_H_ 1
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- gd->bd->bi_baudrate = gd->baudrate;
return 0;
}
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" \\-bd: %p\n", gd->bd);
- printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
printf(" |-bi_memsize: %lx\n", bd->bi_memsize);
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
#endif
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
ulong bi_boot_params; /* where this board expects params */
} bd_t;
memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
- bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#else /* !CONFIG_SYS_GENERIC_BOARD */
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */
bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
memcpy(id, (void *)gd, sizeof(gd_t));
#include <environment.h>
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
addr_sp &= ~0x07;
debug("New Stack Pointer is: %08lx\n", addr_sp);
- gd->bd->bi_baudrate = gd->baudrate;
/* Ram isn't board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
#define _U_BOOT_H_
typedef struct bd_info {
- unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
WATCHDOG_RESET();
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts("Work-around for Erratum A-005434 enabled\n");
+#endif
return 0;
}
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+ if (SVR_SOC_VER(svr) == SVR_T4080) {
+ ccsr_rcpm_t *rcpm =
+ (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+ setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+ FSL_CORENET_DEVDISR2_DTSEC1_9);
+ setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+ setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+ /* It needs SW to disable core4~7 as HW design sake on T4080 */
+ for (i = 4; i < 8; i++)
+ cpu_disable(i);
+
+ /* request core4~7 into PH20 state, prior to entering PCL10
+ * state, all cores in cluster should be placed in PH20 state.
+ */
+ setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+ /* put the 2nd cluster into PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+ }
+#endif
+
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
}
#endif
-void cpu_init_f (void)
+ulong cpu_init_f(void)
{
+ ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+ flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
+ return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
int enable_cluster_l2(void)
{
int i = 0;
- u32 cluster;
+ u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
+ /* only the L2 of first cluster should be enabled as expected on T4080,
+ * but there is no EOC in the first cluster as HW sake, so return here
+ * to skip enabling L2 cache of the 2nd cluster.
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4080)
+ return 0;
+
cluster = in_be32(&gur->tp_cluster[i].lower);
if (cluster & TP_CLUSTER_EOC)
return 0;
}
#endif
+ init_used_tlb_cams();
return 0;
}
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+#ifdef CONFIG_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
+#endif
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
#ifdef CONFIG_CPM2
do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
- "current-speed", bd->bi_baudrate, 1);
+ "current-speed", gd->baudrate, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
#endif
DECLARE_GLOBAL_DATA_PTR;
-void cpu_init_f(void)
+ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
+
+ return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#endif
mtspr HID0,r0
-#ifndef CONFIG_E500MC
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
mtmsr r3
isync
- bl cpu_init_f
+ bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
SECTIONS
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
+ li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
+ CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask(void)
+__weak u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores(void)
+__weak int cpu_numcores(void)
{
struct cpu_type *cpu = gd->arch.cpu;
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
-#define CONFIG_MAX_CPUS 8
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_NUM_FM2_DTSEC 7
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#if defined(CONFIG_PPC_T4160)
+#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#elif defined(CONFIG_PPC_T4080)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
+#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
case SVR_T4160:
+ case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T1040:
return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0);
case SVR_P5040:
return IS_SVR_REV(svr, 1, 0);
}
#if defined(CONFIG_B4860QDS) || \
defined(CONFIG_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
+ defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T1040RDB)
+ defined(CONFIG_T104xRDB)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
+#define SVR_T4080 0x824102
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
CONFIG_ARCH_DEVICE_TREE := sandbox
+
+# Define this to avoid linking with SDL, which requires SDL libraries
+# This can solve 'sdl-config: Command not found' errors
+ifneq ($(NO_SDL),)
+PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
+endif
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SANDBOX_ARCH
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
#include <config.h>
+#define TIMER_BASE_CLK 1000000
+#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
+
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
while (get_timer(start) < ticks) ;
}
-/* initiate and setup timer0 interrupt to 1MHz
+/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
- /* 1ms ticks */
+ /* SYS_HZ ticks per second */
leon2->Timer_Counter_1 = 0;
- leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */
+ leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
leon2->Timer_Control_1 =
(LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD);
return LEON2_TIMER1_IRQNO;
}
+ulong get_tbclk(void)
+{
+ return TIMER_BASE_CLK;
+}
+
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
- /* timer set to 1kHz ==> 1 clk tick = 1 msec */
- if (usec < 1000)
+ if (usec < US_PER_TICK)
return 1;
- return (usec / 1000);
+ return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
- /* 1tick = 1usec */
- return ticks * 1000;
+ return ticks * US_PER_TICK;
}
#include <config.h>
+#define TIMER_BASE_CLK 1000000
+#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
+
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
while (get_timer(start) < ticks) ;
}
-/* initiate and setup timer0 interrupt to 1MHz
+/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
int timer_interrupt_init_cpu(void)
{
- /* 1ms ticks */
+ /* SYS_HZ ticks per second */
gptimer->e[0].val = 0;
- gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */
+ gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
gptimer->e[0].ctrl =
(LEON3_GPTIMER_EN |
LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
return gptimer_irq;
}
+ulong get_tbclk(void)
+{
+ return TIMER_BASE_CLK;
+}
+
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
- /* timer set to 1kHz ==> 1 clk tick = 1 msec */
- if (usec < 1000)
+ if (usec < US_PER_TICK)
return 1;
- return (usec / 1000);
+ return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
- /* 1tick = 1usec */
- return ticks * 1000;
+ return ticks * US_PER_TICK;
}
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
- bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
{
unsigned int reg;
-#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
-#endif
acadia_gpio_init();
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
- board/amcc/bamboo/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amcc/canyonlands/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x20000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x80000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amcc/sequoia/init.o (.text*)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
-Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_fn,
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)&fpga_fns,
0,
+ &spartan3_op,
"3s200aft256"}
};
}
/* Set the FPGA's PROG_B line to the specified level */
-int xilinx_pgm_fn(int assert, int flush, int cookie)
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
-int xilinx_init_fn(int cookie)
+int xilinx_init_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Test the state of the active-high FPGA DONE pin */
-int xilinx_done_fn(int cookie)
+int xilinx_done_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Abort an FPGA operation */
-int xilinx_abort_fn(int cookie)
+int xilinx_abort_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
/* ensure all SPI peripherals and FPGAs are deselected */
return rc;
}
-int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_clk;
}
-int xilinx_wr_fn(int assert_write, int flush, int cookie)
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_write;
}
-int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
- xilinx_pgm_fn,
- xilinx_clk_fn,
- xilinx_init_fn,
- xilinx_done_fn,
- xilinx_wr_fn,
+ xilinx_pgm_config_fn,
+ xilinx_clk_config_fn,
+ xilinx_init_config_fn,
+ xilinx_done_config_fn,
+ xilinx_wr_config_fn,
0,
- xilinx_fastwr_fn
+ xilinx_fastwr_config_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)&xilinx_fns,
- 0}
+ 0,
+ &spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */
* so set stuff here instead of static initialisation:
*/
xilinx_fns.pre = xilinx_pre_config_fn;
- xilinx_fns.pgm = xilinx_pgm_fn;
- xilinx_fns.clk = xilinx_clk_fn;
- xilinx_fns.init = xilinx_init_fn;
- xilinx_fns.done = xilinx_done_fn;
- xilinx_fns.wr = xilinx_wr_fn;
- xilinx_fns.bwr = xilinx_fastwr_fn;
+ xilinx_fns.pgm = xilinx_pgm_config_fn;
+ xilinx_fns.clk = xilinx_clk_config_fn;
+ xilinx_fns.init = xilinx_init_config_fn;
+ xilinx_fns.done = xilinx_done_config_fn;
+ xilinx_fns.wr = xilinx_wr_config_fn;
+ xilinx_fns.bwr = xilinx_fastwr_config_fn;
xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
fpga_add(fpga_xilinx, &xilinx_fpga[i]);
}
return assert_clk;
}
-Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)&balloon3_fpga_fns, 0);
/* Initialize the FPGA */
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/gpio.h>
-#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <spi.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <net.h>
#include <asm/mach-common/bits/bootrom.h>
#include <netdev.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
printf("Entering rescue mode..\n");
#ifdef CONFIG_RANDOM_MACADDR
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- eth_random_enetaddr(enetaddr);
+ eth_random_addr(enetaddr);
if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
printf("Failed to set ethernet address\n");
set_led(LED_ALARM_BLINKING);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifndef RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS 0xfffffffc
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <asm/gpio.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#define USE_SP_CODE
#ifdef USE_SP_CODE
-Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn,
};
#else
-Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
};
#endif
-Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
ngcc_fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
-
- /* Align to next NAND block */
- . = ALIGN(0x4000);
- common/env_embedded.o (.ppcenv)
- /* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ printf("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
+ if (ret) {
+ printf("VID: I2c failed to switch channel to DPM\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* Round up to the value of step of Voltage regulator */
+ voltage = roundup(vdd_target, ZM_STEP);
+ debug("VID: rounded up voltage = %d\n", voltage);
+
+ /* lower the speed to 100kHz to access ZM7300 device */
+ debug("VID: Setting bus speed to 100KHz if not already set\n");
+ orig_i2c_speed = i2c_get_bus_speed();
+ if (orig_i2c_speed != 100000)
+ i2c_set_bus_speed(100000);
+
+ /* Read the existing level on board, if equal to requsted one,
+ no need to re-set */
+ existing_voltage = zm_read_voltage();
+
+ /* allowing the voltage difference of one step 0.0125V acceptable */
+ if ((existing_voltage >= voltage) &&
+ (existing_voltage < (voltage + ZM_STEP))) {
+ debug("VID: voltage already set as requested,returning\n");
+ ret = existing_voltage;
+ goto out;
+ }
+ debug("VID: Changing voltage for board from %dmV to %dmV\n",
+ existing_voltage/10, voltage/10);
+
+ if (zm_disable_wp() < 0) {
+ ret = -1;
+ goto out;
+ }
+ /* Change Voltage: the change is done through all the steps in the
+ way, to avoid reset to the board due to power good signal fail
+ in big voltage change gap jump.
+ */
+ if (existing_voltage > voltage) {
+ temp_voltage = existing_voltage - ZM_STEP;
+ while (temp_voltage >= voltage) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage -= ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping down vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ } else {
+ temp_voltage = existing_voltage + ZM_STEP;
+ while (temp_voltage < (voltage + ZM_STEP)) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage += ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping up vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+
+ if (zm_enable_wp() < 0)
+ ret = -1;
+
+ /* restore the speed to 400kHz */
+out: debug("VID: Restore the I2C bus speed to %dKHz\n",
+ orig_i2c_speed/1000);
+ i2c_set_bus_speed(orig_i2c_speed);
+ if (ret < 0)
+ goto exit;
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_last = read_voltage();
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
int configure_vsc3316_3308(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0) < 0)
+ printf("Warning: Adjusting core voltage failed\n");
+
/* SerDes1 refclks need to be set again, as default clks
* are not suitable for CPRI and onboard SGMIIs to work
* simultaneously.
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
/* some boards with non-256-bytes EEPROM have special define */
/* for MAX_NUM_PORTS in board-specific file */
#ifndef MAX_NUM_PORTS
-#define MAX_NUM_PORTS 23
+#define MAX_NUM_PORTS 16
#endif
#define NXID_VERSION 1
#endif
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
if (read_eeprom()) {
printf("Read failed.\n");
- return -1;
+ return 0;
}
if (!is_valid) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.id[0], e.id[1], e.id[2], e.id[3]);
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
crcp = (void *)&e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 10000, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg = 0x7, vid;
+ uint16_t voltage_read;
+ u8 ret;
+
+ vid = (voltage - 5000) / ZM_STEP;
+
+ ret = zm_write(reg, vid);
+ if (ret != -1) {
+ voltage_read = hex_to_1_10mv[ret];
+ debug("voltage set to %dmV\n", voltage_read/10);
+ return voltage_read;
+ }
+ return -1;
+}
+
+/* zm_read_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_read_voltage(void)
+{
+ u8 reg = 0x7;
+ u8 ret;
+ int voltage;
+
+ ret = zm_read(reg);
+ if (ret != -1) {
+ voltage = hex_to_1_10mv[ret];
+ debug("Voltage read is %dmV\n", voltage/10);
+ return voltage;
+ } else {
+ return -1;
+ }
+}
+
+int zm_disable_wp()
+{
+ u8 new_wp_value;
+
+ /* Disable using Write-Protect register 0x96 */
+ new_wp_value = 0x8;
+ if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
+ printf("Disable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
+int zm_enable_wp()
+{
+ u8 orig_wp_value;
+ orig_wp_value = 0x0;
+
+ /* Enable using Write-Protect register 0x96 */
+ if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
+ printf("Enable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ZM7300_H_
+#define __ZM7300_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define ZM_STEP 125
+int zm7300_set_voltage(int voltage_1_10mv);
+int zm_write_voltage(int voltage);
+int zm_read_voltage(void);
+int zm_disable_wp(void);
+int zm_enable_wp(void);
+
+#endif /* __ZM7300_H_ */
# SPDX-License-Identifier: GPL-2.0+
#
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += p1_p2_rdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
obj-y += ddr.o
obj-y += law.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
+
+endif
phys_size_t fixed_sdram (void)
{
- char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
- } else {
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- }
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
0, 4, BOOKE_PAGESZ_256K, 1),
#endif /* #if defined(CONFIG_PCI) */
+#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1)
get_sys_info(&sys_info);
return sys_info.freq_systembus;
}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+ /*
+ * The QEMU u-boot target only needs to drive the first core,
+ * spinning and device tree nodes get driven by QEMU itself
+ */
+ return 1;
+}
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask(void)
+{
+ return (1 << cpu_numcores()) - 1;
+}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data\n"
+ "rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+
+#include "../common/fman.h"
+#include "t4rdb.h"
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ if (srds_prtcl_s1 == 28) {
+ /* SGMII */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
+ } else {
+ puts("Invalid SerDes1 protocol for T4240RDB\n");
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ if (srds_prtcl_s2 == 56) {
+ /* SGMII && XFI */
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
+ } else {
+ puts("Invalid SerDes2 protocol for T4240RDB\n");
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t4rdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sRDB, ", cpu->name);
+
+ puts("SERDES Reference Clocks:\n");
+ printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
+ " SERDES3=100MHz SERDES4=100MHz\n");
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int rcwsrc;
+
+ /* RCW section SW3[4] */
+ rcwsrc = 0x0;
+ puts("RCW source = ");
+ switch (rcwsrc & 0x1) {
+ case 0x1:
+ puts("SDHC/eMMC\n");
+ break;
+ default:
+ puts("I2C normal addressing\n");
+ break;
+ }
+}
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#slow mdio clock
+095fc030 00008148
+095fd030 00808148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 28_56_2_10
+16070019 18101916 00000000 00000000
+70701050 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000287fc
+00000000 50000000 00000000 00000028
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T4RDB_H__
+#define __T4RDB_H__
+
+#undef CONFIG_SYS_NUM_FM1_DTSEC
+#undef CONFIG_SYS_NUM_FM2_DTSEC
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) &fpga_fns,
#include <common.h>
#include <net.h>
#include <netdev.h>
-#include <asm/net.h>
int checkboard(void)
{
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
int board_early_init_f(void)
{
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
if (ret)
printf("error triggering PCIe FPGA config\n");
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
return ret;
}
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
#define PRSTCFG_POWUP_RST 0x3
void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
void pci_of_setup(void *blob, bd_t *bd);
#
#PBI commands
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-#Freescale's errarta sheet suggests it may be done with PBI
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
09000010 00000000
+091380c0 000009C4
09000014 00000000
+091380c0 000009C4
09000018 81d00000
-09021008 0000f000
-09021028 0000f000
-09021048 0000f000
-09021068 0000f000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
09000018 00000000
+091380c0 000009C4
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
}
#define PCIE_SW_RST 14
-#define PEXHC_SW_RST 13
-#define HOOPER_SW_RST 12
+#define PEXHC_RST 13
+#define HOOPER_RST 12
void pci_init_board(void)
{
- /* first wait for the PCIe FPGA to be configured
+ qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+ /* wait for the PCIe FPGA to be configured
* it has been triggered earlier in board_early_init_r */
- int ret = wait_for_fpga_config();
- if (ret)
+ if (wait_for_fpga_config())
printf("error finishing PCIe FPGA config\n");
qrio_prst(PCIE_SW_RST, false, false);
- qrio_prst(PEXHC_SW_RST, false, false);
- qrio_prst(HOOPER_SW_RST, false, false);
+ qrio_prst(PEXHC_RST, false, false);
+ qrio_prst(HOOPER_RST, false, false);
/* Hooper is not direcly PCIe capable */
mdelay(50);
#define WDMASK_OFF 0x16
-static void qrio_wdmask(u8 bit, bool wden)
+void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}
+
+#define CTRLH_OFF 0x02
+#define CTRLH_WRL_BOOT 0x01
+#define CTRLH_WRL_UNITRUN 0x02
+
+void qrio_set_leds(void)
+{
+ u8 ctrlh;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* set UNIT LED to RED and BOOT LED to ON */
+ ctrlh = in_8(qrio_base + CTRLH_OFF);
+ ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+ out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF 0x03
+#define CTRLL_WRB_BUFENA 0x20
+
+void qrio_enable_app_buffer(void)
+{
+ u8 ctrll;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* enable application buffer */
+ ctrll = in_8(qrio_base + CTRLL_OFF);
+ ctrll |= (CTRLL_WRB_BUFENA);
+ out_8(qrio_base + CTRLL_OFF, ctrll);
+}
#64 bytes RCW data
14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428002
+00000000 00000000 00000000 F0428816
00000000 00000000 00000000 00000000
#include "fpga.h"
#include "mvsmr.h"
-Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
0
};
-Xilinx_desc spartan3 = {
- Xilinx_Spartan2,
+xilinx_desc spartan3 = {
+ xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) &fpga_fns,
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* update "memory" property in the blob
*/
/* baudrate */
nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
if (nodeoffset >= 0) {
- speed = cpu_to_be32 (bd->bi_baudrate);
+ speed = cpu_to_be32 (gd->baudrate);
ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
sizeof (unsigned long));
if (ret < 0)
u32 BoardType = get_BoardType ();
char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
char *p;
- bd_t *bd = gd->bd;
hw_watchdog_reset ();
if ((p = getenv ("console_nr")) != NULL) {
unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
- bd->bi_baudrate &= ~3;
- bd->bi_baudrate |= con_nr & 3;
+ gd->baudrate &= ~3;
+ gd->baudrate |= con_nr & 3;
}
return 0;
}
--- /dev/null
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Native Execution of U-Boot
+==========================
+
+The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
+almost any hardware. To achieve this it builds U-Boot (so far as possible)
+as a normal C application with a main() and normal C libraries.
+
+All of U-Boot's architecture-specific code therefore cannot be built as part
+of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
+all the generic code, not specific to any one architecture. The idea is to
+create unit tests which we can run to test this upper level code.
+
+CONFIG_SANDBOX is defined when building a native board.
+
+The chosen vendor and board names are also 'sandbox', so there is a single
+board in board/sandbox/sandbox.
+
+CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
+machines.
+
+Note that standalone/API support is not available at present.
+
+
+Basic Operation
+---------------
+
+To run sandbox U-Boot use something like:
+
+ make sandbox_config all
+ ./u-boot
+
+Note:
+ If you get errors about 'sdl-config: Command not found' you may need to
+ install libsdl1.2-dev or similar to get SDL support. Alternatively you can
+ build sandbox without SDL (i.e. no display/keyboard support) by removing
+ the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:
+
+ make sandbox_config all NO_SDL=1
+ ./u-boot
+
+
+U-Boot will start on your computer, showing a sandbox emulation of the serial
+console:
+
+
+U-Boot 2014.04 (Mar 20 2014 - 19:06:00)
+
+DRAM: 128 MiB
+Using default environment
+
+In: serial
+Out: lcd
+Err: lcd
+=>
+
+You can issue commands as your would normally. If the command you want is
+not supported you can add it to include/configs/sandbox.h.
+
+To exit, type 'reset' or press Ctrl-C.
+
+
+Console / LCD support
+---------------------
+
+Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+sandbox with LCD and keyboard emulation, using something like:
+
+ ./u-boot -d u-boot.dtb -l
+
+This will start U-Boot with a window showing the contents of the LCD. If
+that window has the focus then you will be able to type commands as you
+would on the console. You can adjust the display settings in the device
+tree file - see arch/sandbox/dts/sandbox.dts.
+
+
+Command-line Options
+--------------------
+
+Various options are available, mostly for test purposes. Use -h to see
+available options. Some of these are described below.
+
+The terminal is normally in what is called 'raw-with-sigs' mode. This means
+that you can use arrow keys for command editing and history, but if you
+press Ctrl-C, U-Boot will exit instead of handling this as a keypress.
+
+Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked'
+(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C
+will exit).
+
+As mentioned above, -l causes the LCD emulation window to be shown.
+
+A device tree binary file can be provided with -d. If you edit the source
+(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to
+recreate the binary file.
+
+To execute commands directly, use the -c option. You can specify a single
+command, or multiple commands separated by a semicolon, as is normal in
+U-Boot. Be careful with quoting as the shall will normally process and
+swallow quotes. When -c is used, U-Boot exists after the command is complete,
+but you can force it to go to interactive mode instead with -i.
+
+
+Memory Emulation
+----------------
+
+Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE.
+The -m option can be used to read memory from a file on start-up and write
+it when shutting down. This allows preserving of memory contents across
+test runs. You can tell U-Boot to remove the memory file after it is read
+(on start-up) with the --rm_memory option.
+
+To access U-Boot's emulated memory within the code, use map_sysmem(). This
+function is used throughout U-Boot to ensure that emulated memory is used
+rather than the U-Boot application memory. This provides memory starting
+at 0 and extending to the size of the emulation.
+
+
+Storing State
+-------------
+
+With sandbox you can write drivers which emulate the operation of drivers on
+real devices. Some of these drivers may want to record state which is
+preserved across U-Boot runs. This is particularly useful for testing. For
+example, the contents of a SPI flash chip should not disappear just because
+U-Boot exits.
+
+State is stored in a device tree file in a simple format which is driver-
+specific. You then use the -s option to specify the state file. Use -r to
+make U-Boot read the state on start-up (otherwise it starts empty) and -w
+to write it on exit (otherwise the stored state is left unchanged and any
+changes U-Boot made will be lost). You can also use -n to tell U-Boot to
+ignore any problems with missing state. This is useful when first running
+since the state file will be empty.
+
+The device tree file has one node for each driver - the driver can store
+whatever properties it likes in there. See 'Writing Sandbox Drivers' below
+for more details on how to get drivers to read and write their state.
+
+
+Running and Booting
+-------------------
+
+Since there is no machine architecture, sandbox U-Boot cannot actually boot
+a kernel, but it does support the bootm command. Filesystems, memory
+commands, hashing, FIT images, verified boot and many other features are
+supported.
+
+When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real
+machine. Of course in this case, no kernel is run.
+
+It is also possible to tell U-Boot that it has jumped from a temporary
+previous U-Boot binary, with the -j option. That binary is automatically
+removed by the U-Boot that gets the -j option. This allows you to write
+tests which emulate the action of chain-loading U-Boot, typically used in
+a situation where a second 'updatable' U-Boot is stored on your board. It
+is very risky to overwrite or upgrade the only U-Boot on a board, since a
+power or other failure will brick the board and require return to the
+manufacturer in the case of a consumer device.
+
+
+Supported Drivers
+-----------------
+
+U-Boot sandbox supports these emulations:
+
+- Block devices
+- Chrome OS EC
+- GPIO
+- Host filesystem (access files on the host from within U-Boot)
+- Keyboard (Chrome OS)
+- LCD
+- Serial (for console only)
+- Sound (incomplete - see sandbox_sdl_sound_init() for details)
+- SPI
+- SPI flash
+- TPM (Trusted Platform Module)
+
+Notable omissions are networking and I2C.
+
+A wide range of commands is implemented. Filesystems which use a block
+device are supported.
+
+Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
+driver model (CONFIG_DM) and associated commands.
+
+
+SPI Emulation
+-------------
+
+Sandbox supports SPI and SPI flash emulation.
+
+This is controlled by the spi_sf argument, the format of which is:
+
+ bus:cs:device:file
+
+ bus - SPI bus number
+ cs - SPI chip select number
+ device - SPI device emulation name
+ file - File on disk containing the data
+
+For example:
+
+ dd if=/dev/zero of=spi.bin bs=1M count=4
+ ./u-boot --spi_sf 0:0:M25P16:spi.bin
+
+With this setup you can issue SPI flash commands as normal:
+
+=>sf probe
+SF: Detected M25P16 with page size 64 KiB, total 2 MiB
+=>sf read 0 0 10000
+SF: 65536 bytes @ 0x0 Read: OK
+=>
+
+Since this is a full SPI emulation (rather than just flash), you can
+also use low-level SPI commands:
+
+=>sspi 0:0 32 9f
+FF202015
+
+This is issuing a READ_ID command and getting back 20 (ST Micro) part
+0x2015 (the M25P16).
+
+Drivers are connected to a particular bus/cs using sandbox's state
+structure (see the 'spi' member). A set of operations must be provided
+for each driver.
+
+
+Configuration settings for the curious are:
+
+CONFIG_SANDBOX_SPI_MAX_BUS
+ The maximum number of SPI buses supported by the driver (default 1).
+
+CONFIG_SANDBOX_SPI_MAX_CS
+ The maximum number of chip selects supported by the driver
+ (default 10).
+
+CONFIG_SPI_IDLE_VAL
+ The idle value on the SPI bus
+
+
+Writing Sandbox Drivers
+-----------------------
+
+Generally you should put your driver in a file containing the word 'sandbox'
+and put it in the same directory as other drivers of its type. You can then
+implement the same hooks as the other drivers.
+
+To access U-Boot's emulated memory, use map_sysmem() as mentioned above.
+
+If your driver needs to store configuration or state (such as SPI flash
+contents or emulated chip registers), you can use the device tree as
+described above. Define handlers for this with the SANDBOX_STATE_IO macro.
+See arch/sandbox/include/asm/state.h for documentation. In short you provide
+a node name, compatible string and functions to read and write the state.
+Since writing the state can expand the device tree, you may need to use
+state_setprop() which does this automatically and avoids running out of
+space. See existing code for examples.
+
+
+Testing
+-------
+
+U-Boot sandbox can be used to run various tests, mostly in the test/
+directory. These include:
+
+ command_ut
+ - Unit tests for command parsing and handling
+ compression
+ - Unit tests for U-Boot's compression algorithms, useful for
+ security checking. It supports gzip, bzip2, lzma and lzo.
+ driver model
+ - test/dm/test-dm.sh to run these.
+ image
+ - Unit tests for images:
+ test/image/test-imagetools.sh - multi-file images
+ test/image/test-fit.py - FIT images
+ tracing
+ - test/trace/test-trace.sh tests the tracing system (see README.trace)
+ verified boot
+ - See test/vboot/vboot_test.sh for this
+
+If you change or enhance any of the above subsystems, you shold write or
+expand a test and include it with your patch series submission. Test
+coverage in U-Boot is limited, as we need to work to improve it.
+
+Note that many of these tests are implemented as commands which you can
+run natively on your board if desired (and enabled).
+
+It would be useful to have a central script to run all of these.
+
+--
+Simon Glass <sjg@chromium.org>
+Updated 22-Mar-14
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-Native Execution of U-Boot
-==========================
-
-The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
-almost any hardware. To achieve this it builds U-Boot (so far as possible)
-as a normal C application with a main() and normal C libraries.
-
-All of U-Boot's architecture-specific code therefore cannot be built as part
-of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
-all the generic code, not specific to any one architecture. The idea is to
-create unit tests which we can run to test this upper level code.
-
-CONFIG_SANDBOX is defined when building a native board.
-
-The chosen vendor and board names are also 'sandbox', so there is a single
-board in board/sandbox/sandbox.
-
-CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
-machines.
-
-Note that standalone/API support is not available at present.
-
-The serial driver is a very simple implementation which reads and writes to
-the console. It does not set the terminal into raw mode, so cursor keys and
-history will not work yet.
-
-
-SPI Emulation
--------------
-
-Sandbox supports SPI and SPI flash emulation.
-
-This is controlled by the spi_sf argument, the format of which is:
-
- bus:cs:device:file
-
- bus - SPI bus number
- cs - SPI chip select number
- device - SPI device emulation name
- file - File on disk containing the data
-
-For example:
-
- dd if=/dev/zero of=spi.bin bs=1M count=4
- ./u-boot --spi_sf 0:0:M25P16:spi.bin
-
-With this setup you can issue SPI flash commands as normal:
-
-=>sf probe
-SF: Detected M25P16 with page size 64 KiB, total 2 MiB
-=>sf read 0 0 10000
-SF: 65536 bytes @ 0x0 Read: OK
-=>
-
-Since this is a full SPI emulation (rather than just flash), you can
-also use low-level SPI commands:
-
-=>sspi 0:0 32 9f
-FF202015
-
-This is issuing a READ_ID command and getting back 20 (ST Micro) part
-0x2015 (the M25P16).
-
-Drivers are connected to a particular bus/cs using sandbox's state
-structure (see the 'spi' member). A set of operations must be provided
-for each driver.
-
-
-Configuration settings for the curious are:
-
-CONFIG_SANDBOX_SPI_MAX_BUS
- The maximum number of SPI buses supported by the driver (default 1).
-
-CONFIG_SANDBOX_SPI_MAX_CS
- The maximum number of chip selects supported by the driver
- (default 10).
-
-CONFIG_SPI_IDLE_VAL
- The idle value on the SPI bus
-
-
-Tests
------
-
-So far we have no tests, but when we do these will be documented here.
return assert_write;
}
-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_post_config_fn,
};
-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
};
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
+ eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
-#include <asm/net.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
- bfin_gen_rand_mac(enetaddr);
+ eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)&mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
/* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
int board_init(void)
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SECURE_BOOT T208xRDB:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4rdb T4160RDB T4240RDB:PPC_T4160 Chunhe Lan <Chunhe.Lan@freescale.com>
+Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan <Chunhe.Lan@freescale.com>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
+Active sandbox sandbox - - sandbox sandbox - Simon Glass <sjg@chromium.org>
Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
Active sh sh2 - renesas rsk7269 rsk7269 - -
static int show_dram_config(void)
{
- ulong size;
+ unsigned long long size;
#ifdef CONFIG_NR_DRAM_BANKS
int i;
}
#endif
-static int setup_baud_rate(void)
-{
- /* Ick, can we get rid of this line? */
- gd->bd->bi_baudrate = gd->baudrate;
-
- return 0;
-}
-
static int setup_dram_config(void)
{
/* Ram is board specific, so move it to board code ... */
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
#endif
- setup_baud_rate,
display_new_sp,
#ifdef CONFIG_SYS_EXTBDINFO
setup_board_extra,
void board_init_f(ulong boot_flags)
{
-#ifndef CONFIG_X86
+#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA
+ /*
+ * For some archtectures, global data is initialized and used before
+ * calling this function. The data should be preserved. For others,
+ * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack
+ * here to host global data until relocation.
+ */
gd_t data;
gd = &data;
-#endif
/*
* Clear global data before it is accessed at debug print
* in initcall_run_list. Otherwise the debug print probably
* get the wrong vaule of gd->have_console.
*/
-#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
- !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
- !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
zero_global_data();
#endif
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("IP addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %6u bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
board_detail();
return 0;
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
#if defined(CONFIG_CMD_NET)
print_eths();
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %6u bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
#if defined(CONFIG_CMD_NET)
print_eths();
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %u bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", gd->baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %d bps\n", gd->baudrate);
return 0;
}
image_buf = map_sysmem(image_start, image_len);
switch (comp) {
case IH_COMP_NONE:
- if (load == blob_start || load == image_start) {
+ if (load == image_start) {
printf(" XIP %s ... ", type_name);
no_overlap = 1;
} else {
#include <watchdog.h>
#include <linux/stddef.h>
#include <asm/byteorder.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int argc, char * const argv[])
{
char buf[32];
- char *addr, *cmd, *res;
+ ulong addr;
+ char *ptr, *cmd, *res;
size_t size = 0;
ssize_t len;
env_t *envp;
if (argc < 1)
return CMD_RET_USAGE;
- addr = (char *)simple_strtoul(argv[0], NULL, 16);
+ addr = simple_strtoul(argv[0], NULL, 16);
+ ptr = map_sysmem(addr, size);
if (size)
- memset(addr, '\0', size);
+ memset(ptr, '\0', size);
argc--;
argv++;
if (sep) { /* export as text file */
len = hexport_r(&env_htab, sep,
H_MATCH_KEY | H_MATCH_IDENT,
- &addr, size, argc, argv);
+ &ptr, size, argc, argv);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return 0;
}
- envp = (env_t *)addr;
+ envp = (env_t *)ptr;
if (chk) /* export as checksum protected block */
res = (char *)envp->data;
else /* export as raw binary data */
- res = addr;
+ res = ptr;
len = hexport_r(&env_htab, '\0',
H_MATCH_KEY | H_MATCH_IDENT,
static int do_env_import(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- char *cmd, *addr;
+ ulong addr;
+ char *cmd, *ptr;
char sep = '\n';
int chk = 0;
int fmt = 0;
if (!fmt)
printf("## Warning: defaulting to text format\n");
- addr = (char *)simple_strtoul(argv[0], NULL, 16);
+ addr = simple_strtoul(argv[0], NULL, 16);
+ ptr = map_sysmem(addr, 0);
if (argc == 2) {
size = simple_strtoul(argv[1], NULL, 16);
puts("## Error: external checksum format must pass size\n");
return CMD_RET_FAILURE;
} else {
- char *s = addr;
+ char *s = ptr;
size = 0;
if (chk) {
uint32_t crc;
- env_t *ep = (env_t *)addr;
+ env_t *ep = (env_t *)ptr;
size -= offsetof(env_t, data);
memcpy(&crc, &ep->crc, sizeof(crc));
puts("## Error: bad CRC, import failed\n");
return 1;
}
- addr = (char *)ep->data;
+ ptr = (char *)ep->data;
}
- if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR,
- 0, NULL) == 0) {
+ if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR, 0,
+ NULL) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
printf("\ntime:");
if (minutes)
printf(" %lu minutes,", minutes);
- printf(" %lu.%03lu seconds, %lu ticks\n",
- seconds, milliseconds, cycles);
+ printf(" %lu.%03lu seconds\n", seconds, milliseconds);
}
static int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
i->p = the_command;
#else
int n;
- static char the_command[CONFIG_SYS_CBSIZE];
+ static char the_command[CONFIG_SYS_CBSIZE + 1];
#ifdef CONFIG_BOOT_RETRY_TIME
# ifndef CONFIG_RESET_TO_RETRY
return 1;
}
- if (run_command(arg, flag) != 0)
+ if (run_command_list(arg, -1, flag) != 0)
return 1;
}
return 0;
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- return;
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return;
+ } else {
+ printf("%s: *** Using Backup GPT ***\n",
+ __func__);
+ }
}
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- return -1;
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return -1;
+ } else {
+ printf("%s: *** Using Backup GPT ***\n",
+ __func__);
+ }
}
if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
!= pte_blk_cnt)
goto err;
- /* recalculate the values for the Second GPT Header */
+ /* recalculate the values for the Backup GPT Header */
val = le64_to_cpu(gpt_h->my_lba);
gpt_h->my_lba = gpt_h->alternate_lba;
gpt_h->alternate_lba = cpu_to_le64(val);
Background
----------
-U-Boot has tranditionally had a board.c file for each architecture. This has
+U-Boot has traditionally had a board.c file for each architecture. This has
introduced quite a lot of duplication, with each architecture tending to do
initialisation slightly differently. To address this, a new 'generic board
init' feature was introduced a year ago in March 2013 (further motivation is
|Partition n |
| |
----------------------------------------------------------
- LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Secondary
- -------------------------------------------------- (bkp)
- LBA -33 |Entries 5 - 128 | GPT
+ LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Backup
+ -------------------------------------------------- GPT
+ LBA -33 |Entries 5 - 128 |
| |
| |
LBA -2 | |
--------------------------------------------------
- LBA -1 |Secondary GPT Header |
+ LBA -1 |Backup GPT Header |
----------------------------------------------------------
For a legacy reasons, GPT's LBA 0 sector has a MBR structure. It is called
"LBA -1" means the last addressable block (in the mmc subsystem:
"dev_desc->lba - 1")
-Primary/Secondary GPT header:
+Primary/Backup GPT header:
----------------------------
Offset Size Description
GPT headers and partition entries are protected by CRC32 (the POSIX CRC32).
-Primary GPT header and Secondary GPT header have swapped values of "Current LBA"
+Primary GPT header and Backup GPT header have swapped values of "Current LBA"
and "Backup LBA" and therefore different CRC32 check-sum.
CRC32 for GPT headers (field "CRC of header") are calculated up till
the whole array entry ( Number_of_partition_entries *
sizeof(partition_entry_size (usually 128)))
-Observe, how Secondary GPT is placed in the memory. It is NOT a mirror reflect
+Observe, how Backup GPT is placed in the memory. It is NOT a mirror reflect
of the Primary.
Partition Entry Format:
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(xilinx_desc *desc ); */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(xilinx_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Spartan2_ss_load (desc, buf, bsize);
+ ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Spartan2_sp_load (desc, buf, bsize);
+ ret_val = spartan2_sp_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Spartan2_ss_dump (desc, buf, bsize);
+ ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Spartan2_sp_dump (desc, buf, bsize);
+ ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan2_info( Xilinx_desc *desc )
+static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
return ret_val;
}
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
/* ------------------------------------------------------------------------- */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
+ xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
return ret_val;
}
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan2_op = {
+ .load = spartan2_load,
+ .dump = spartan2_dump,
+ .info = spartan2_info,
+};
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_sp_info(xilinx_desc *desc ); */
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_ss_info(Xilinx_desc *desc); */
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_ss_info(xilinx_desc *desc); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Spartan3_ss_load (desc, buf, bsize);
+ ret_val = spartan3_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Spartan3_sp_load (desc, buf, bsize);
+ ret_val = spartan3_sp_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Spartan3_ss_dump (desc, buf, bsize);
+ ret_val = spartan3_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Spartan3_sp_dump (desc, buf, bsize);
+ ret_val = spartan3_sp_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Spartan3_info( Xilinx_desc *desc )
+static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
return ret_val;
}
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
/* ------------------------------------------------------------------------- */
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
- Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
+ xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
return ret_val;
}
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan3_op = {
+ .load = spartan3_load,
+ .dump = spartan3_dump,
+ .info = spartan3_info,
+};
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn);
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
return ret_val;
}
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
/* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+ .load = virtex2_load,
+ .dump = virtex2_dump,
+ .info = virtex2_info,
+};
#include <spartan3.h>
#include <zynqpl.h>
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* Define FPGA_DEBUG to get debug printf's */
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
/* Local Static Functions */
-static int xilinx_validate (Xilinx_desc * desc, char *fn);
+static int xilinx_validate(xilinx_desc *desc, char *fn);
/* ------------------------------------------------------------------------- */
unsigned char *dataptr;
unsigned int i;
const fpga_desc *desc;
- Xilinx_desc *xdesc;
+ xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata;
/* Find out fpga_description */
return FPGA_FAIL;
}
} else {
- printf("%s: Please fill correct device ID to Xilinx_desc\n",
+ printf("%s: Please fill correct device ID to xilinx_desc\n",
__func__);
}
printf(" part number = \"%s\"\n", buffer);
return fpga_load(devnum, dataptr, swapsize);
}
-int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL; /* assume a failure */
-
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- PRINTF ("%s: Launching the Spartan-II Loader...\n",
- __FUNCTION__);
- ret_val = Spartan2_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- PRINTF ("%s: Launching the Spartan-III Loader...\n",
- __FUNCTION__);
- ret_val = Spartan3_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
- PRINTF ("%s: Launching the Virtex-II Loader...\n",
- __FUNCTION__);
- ret_val = Virtex2_load (desc, buf, bsize);
-#else
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- PRINTF("%s: Launching the Zynq PL Loader...\n",
- __func__);
- ret_val = zynq_load(desc, buf, bsize);
-#else
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- break;
-
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
+ return FPGA_FAIL;
+ }
- return ret_val;
+ return desc->operations->load(desc, buf, bsize);
}
-int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL; /* assume a failure */
-
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- PRINTF ("%s: Launching the Spartan-II Reader...\n",
- __FUNCTION__);
- ret_val = Spartan2_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- PRINTF ("%s: Launching the Spartan-III Reader...\n",
- __FUNCTION__);
- ret_val = Spartan3_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined( CONFIG_FPGA_VIRTEX2)
- PRINTF ("%s: Launching the Virtex-II Reader...\n",
- __FUNCTION__);
- ret_val = Virtex2_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- PRINTF("%s: Launching the Zynq PL Reader...\n",
- __func__);
- ret_val = zynq_dump(desc, buf, bsize);
-#else
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- break;
-
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
+ return FPGA_FAIL;
+ }
- return ret_val;
+ return desc->operations->dump(desc, buf, bsize);
}
-int xilinx_info (Xilinx_desc * desc)
+int xilinx_info(xilinx_desc *desc)
{
int ret_val = FPGA_FAIL;
if (xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
- case Xilinx_Spartan2:
+ case xilinx_spartan2:
printf ("Spartan-II\n");
break;
- case Xilinx_Spartan3:
+ case xilinx_spartan3:
printf ("Spartan-III\n");
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
printf ("Virtex-II\n");
break;
case xilinx_zynq:
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
- switch (desc->family) {
- case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
- Spartan2_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Spartan-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
- Spartan3_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Spartan-III devices.\n",
- __FUNCTION__);
-#endif
- break;
- case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
- Virtex2_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for Virtex-II devices.\n",
- __FUNCTION__);
-#endif
- break;
- case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
- zynq_info(desc);
-#else
- /* just in case */
- printf("%s: No support for Zynq devices.\n",
- __func__);
-#endif
- /* Add new family types here */
- default:
- /* we don't need a message here - we give one up above */
- ;
- }
+ desc->operations->info(desc);
} else
printf ("No Device Function Table.\n");
/* ------------------------------------------------------------------------- */
-static int xilinx_validate (Xilinx_desc * desc, char *fn)
+static int xilinx_validate(xilinx_desc *desc, char *fn)
{
int ret_val = false;
#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
-int zynq_info(Xilinx_desc *desc)
+static int zynq_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
}
/* Loop can be huge - support CTRL + C */
if (ctrlc())
- return 0;
+ return NULL;
}
- return 0;
+ return NULL;
}
-
-int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 i, control, isr_status, status, swap, diff;
- u32 *buf_start;
-
- /* Detect if we are going working with partial or full bitstream */
- if (bsize != desc->size) {
- printf("%s: Working with partial bitstream\n", __func__);
- partialbit = 1;
- }
+ unsigned long ts;
+ u32 isr_status;
- buf_start = check_data((u8 *)buf, bsize, &swap);
- if (!buf_start)
- return FPGA_FAIL;
-
- /* Check if data is postpone from start */
- diff = (u32)buf_start - (u32)buf;
- if (diff) {
- printf("%s: Bitstream is not validated yet (diff %x)\n",
- __func__, diff);
- return FPGA_FAIL;
- }
+ /* Set up the transfer */
+ writel((u32)srcbuf, &devcfg_base->dma_src_addr);
+ writel(dstbuf, &devcfg_base->dma_dst_addr);
+ writel(srclen, &devcfg_base->dma_src_len);
+ writel(dstlen, &devcfg_base->dma_dst_len);
- if ((u32)buf < SZ_1M) {
- printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
- __func__, (u32)buf);
- return FPGA_FAIL;
- }
+ isr_status = readl(&devcfg_base->int_sts);
- if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
- u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
+ if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
+ debug("%s: Error: isr = 0x%08X\n", __func__,
+ isr_status);
+ debug("%s: Write count = 0x%08X\n", __func__,
+ readl(&devcfg_base->write_count));
+ debug("%s: Read count = 0x%08X\n", __func__,
+ readl(&devcfg_base->read_count));
- /*
- * This might be dangerous but permits to flash if
- * ARCH_DMA_MINALIGN is greater than header size
- */
- if (new_buf > buf_start) {
- debug("%s: Aligned buffer is after buffer start\n",
- __func__);
- new_buf -= ARCH_DMA_MINALIGN;
+ return FPGA_FAIL;
}
+ if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+ printf("%s: Timeout wait for DMA to complete\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
- printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
- (u32)buf_start, (u32)new_buf, swap);
-
- for (i = 0; i < (bsize/4); i++)
- new_buf[i] = load_word(&buf_start[i], swap);
-
- swap = SWAP_DONE;
- buf = new_buf;
- } else if (swap != SWAP_DONE) {
- /* For bitstream which are aligned */
- u32 *new_buf = (u32 *)buf;
+ debug("%s: DMA transfer is done\n", __func__);
- printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
- swap);
+ /* Clear out the DMA status */
+ writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
- for (i = 0; i < (bsize/4); i++)
- new_buf[i] = load_word(&buf_start[i], swap);
+ return FPGA_SUCCESS;
+}
- swap = SWAP_DONE;
- }
+static int zynq_dma_xfer_init(u32 partialbit)
+{
+ u32 status, control, isr_status;
+ unsigned long ts;
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
}
+ return FPGA_SUCCESS;
+}
+
+static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+ u32 *new_buf;
+ u32 i;
+
+ if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+ new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+
+ /*
+ * This might be dangerous but permits to flash if
+ * ARCH_DMA_MINALIGN is greater than header size
+ */
+ if (new_buf > buf) {
+ debug("%s: Aligned buffer is after buffer start\n",
+ __func__);
+ new_buf -= ARCH_DMA_MINALIGN;
+ }
+ printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
+ (u32)buf, (u32)new_buf, swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+
+ buf = new_buf;
+ } else if (swap != SWAP_DONE) {
+ /* For bitstream which are aligned */
+ u32 *new_buf = (u32 *)buf;
+
+ printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+ swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+ }
+
+ return buf;
+}
+
+static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
+ size_t bsize, u32 blocksize, u32 *swap,
+ u32 *partialbit)
+{
+ u32 *buf_start;
+ u32 diff;
+
+ /* Detect if we are going working with partial or full bitstream */
+ if (bsize != desc->size) {
+ printf("%s: Working with partial bitstream\n", __func__);
+ *partialbit = 1;
+ }
+ buf_start = check_data((u8 *)buf, blocksize, swap);
+
+ if (!buf_start)
+ return FPGA_FAIL;
+
+ /* Check if data is postpone from start */
+ diff = (u32)buf_start - (u32)buf;
+ if (diff) {
+ printf("%s: Bitstream is not validated yet (diff %x)\n",
+ __func__, diff);
+ return FPGA_FAIL;
+ }
+
+ if ((u32)buf < SZ_1M) {
+ printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+ __func__, (u32)buf);
+ return FPGA_FAIL;
+ }
+
+ if (zynq_dma_xfer_init(*partialbit))
+ return FPGA_FAIL;
+
+ return 0;
+}
+
+
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ unsigned long ts; /* Timestamp */
+ u32 partialbit = 0;
+ u32 isr_status, swap;
+
+ /*
+ * send bsize inplace of blocksize as it was not a bitstream
+ * in chunks
+ */
+ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
+ &partialbit))
+ return FPGA_FAIL;
+
+ buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
+
debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
debug("%s: Size = %zu\n", __func__, bsize);
flush_dcache_range((u32)buf, (u32)buf +
roundup(bsize, ARCH_DMA_MINALIGN));
- /* Set up the transfer */
- writel((u32)buf | 1, &devcfg_base->dma_src_addr);
- writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
- writel(bsize >> 2, &devcfg_base->dma_src_len);
- writel(0, &devcfg_base->dma_dst_len);
+ if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
+ return FPGA_FAIL;
isr_status = readl(&devcfg_base->int_sts);
-
- /* Polling the PCAP_INIT status for Set */
- ts = get_timer(0);
- while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
- if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
- debug("%s: Error: isr = 0x%08X\n", __func__,
- isr_status);
- debug("%s: Write count = 0x%08X\n", __func__,
- readl(&devcfg_base->write_count));
- debug("%s: Read count = 0x%08X\n", __func__,
- readl(&devcfg_base->read_count));
-
- return FPGA_FAIL;
- }
- if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
- printf("%s: Timeout wait for DMA to complete\n",
- __func__);
- return FPGA_FAIL;
- }
- isr_status = readl(&devcfg_base->int_sts);
- }
-
- debug("%s: DMA transfer is done\n", __func__);
-
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
debug("%s: FPGA config done\n", __func__);
- /* Clear out the DMA status */
- writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
-
if (!partialbit)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
-int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op zynq_op = {
+ .load = zynq_load,
+ .dump = zynq_dump,
+ .info = zynq_info,
+};
*/
#define TWSI_FREQUENCY(m, n) \
- ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
-
-/*
- * These are required to be reprogrammed before enabling the controller
- * because a reset loses them.
- * Default values come from the spec, but a twsi_reset will change them.
- * twsi_slave_address left uninitialized lest checkpatch.pl complains.
- */
-
-/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
-static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
-/* Default frequency corresponding to default m=4, n=4 */
-static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
-/* Default slave address is 0 (so is an uninitialized static) */
-static u8 twsi_slave_address;
+ (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
/*
* Reset controller.
* Controller reset also resets the baud rate and slave address, so
* re-establish them.
*/
-static void twsi_reset(void)
+static void twsi_reset(u8 baud_rate, u8 slave_address)
{
/* ensure controller will be enabled by any twsi*() function */
twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
/* wait 2 ms -- this is what the Marvell LSP does */
udelay(20000);
/* set baud rate */
- writel(twsi_baud_rate, &twsi->baudrate);
+ writel(baud_rate, &twsi->baudrate);
/* set slave address even though we don't use it */
- writel(twsi_slave_address, &twsi->slave_address);
+ writel(slave_address, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* assert STOP but don't care for the result */
(void) twsi_stop(0);
}
}
}
- /* save baud rate and slave for later calls to twsi_reset */
- twsi_baud_rate = baud;
- twsi_actual_speed = highest_speed;
- twsi_slave_address = slaveadd;
/* reset controller */
- twsi_reset();
+ twsi_reset(baud, slaveadd);
}
/*
break;
}
#ifdef DEBUG
- zynq_i2c_debug_status(zynq_i2c));
+ zynq_i2c_debug_status(zynq_i2c);
#endif
/* Clear interrupt status flags */
writel(int_status & mask, &zynq_i2c->interrupt_status);
clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
#ifdef DEBUG
- zynq_i2c_debug_status();
+ zynq_i2c_debug_status(zynq_i2c);
#endif
return 0;
}
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
if (!phydev)
return -1;
+ phy_connect_dev(phydev, dev);
+
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
if (!is_valid_ether_addr(dev->enetaddr)) {
#ifdef CONFIG_RANDOM_MACADDR
printf("Bad MAC address (uninitialized EEPROM?), randomizing\n");
- eth_random_enetaddr(dev->enetaddr);
+ eth_random_addr(dev->enetaddr);
printf("MAC: %pM\n", dev->enetaddr);
#else
printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
dev->recv = ftmac110_recv;
if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
- eth_random_enetaddr(dev->enetaddr);
+ eth_random_addr(dev->enetaddr);
/* allocate tx descriptors (it must be 16 bytes aligned) */
chip->txd = dma_alloc_coherent(
regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
- genphy_config_aneg(phydev);
-
- phy_reset(phydev);
+ phydev->supported = phydev->drv->features;
return 0;
}
#include <phy.h>
#include <errno.h>
#include <linux/err.h>
+#include <linux/compiler.h>
/* Generic PHY support and helper functions */
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
#define MIIM_VSC8514_18G_QSGMII 0x80e0
#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV 0x16
+#define MIIM_VSC8664_EPHY_CON 0x17
+#define MIIM_VSC8664_LED_CON 0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
+
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
return 0;
}
+static int vsc8664_config(struct phy_device *phydev)
+{
+ u32 val;
+
+ /* Enable MAC interface auto-negotiation */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+ val |= (1 << 13);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_EXTENDED);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+ val |= (1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+ /* Enable LED blink */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+ val &= ~(1 << 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static struct phy_driver VSC8211_driver = {
.name = "Vitesse VSC8211",
.uid = 0xfc4b0,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8664_driver = {
+ .name = "Vitesse VSC8664",
+ .uid = 0x70660,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8664_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
/* Vitesse bought Cicada, so we'll put these here */
static struct phy_driver cis8201_driver = {
.name = "CIS8201",
phy_register(&VSC8574_driver);
phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
+ phy_register(&VSC8664_driver);
phy_register(&cis8201_driver);
phy_register(&cis8204_driver);
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
};
#define MAX_I2C_RETRY 3
-int tps6586x_read(int reg)
+static int tps6586x_read(int reg)
{
int i;
uchar data;
return retval;
}
-int tps6586x_write(int reg, uchar *data, uint len)
+static int tps6586x_write(int reg, uchar *data, uint len)
{
int i;
int retval = -1;
#include "asm/immap_qe.h"
#include "qe.h"
+#define MPC85xx_DEVDISR_QE_DISABLE 0x1
+
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
-
+#ifdef CONFIG_DEEP_SLEEP
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
if (!firmware) {
printf("Invalid address\n");
return -EINVAL;
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
return -EPERM;
}
#if defined(CONFIG_K2HK_EVM)
#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
+#undef UART_MCRVAL
+#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
+#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
+#else
+#define UART_MCRVAL (UART_MCR_RTS)
+#endif
#endif
#ifndef CONFIG_SYS_NS16550_IER
}
gd->baudrate = baudrate;
-#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
- gd->bd->bi_baudrate = baudrate;
-#endif
serial_setbrg();
unsigned char c;
int ret, saved_baud, b;
struct serial_device *saved_dev, *s;
- bd_t *bd = gd->bd;
/* Save current serial state */
ret = 0;
saved_dev = serial_current;
- saved_baud = bd->bi_baudrate;
+ saved_baud = gd->baudrate;
for (s = serial_devices; s; s = s->next) {
/* If this driver doesn't support loop back, skip it */
/* Test every available baud rate */
for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
- bd->bi_baudrate = bauds[b];
+ gd->baudrate = bauds[b];
serial_setbrg();
/*
done:
/* Restore previous serial state */
serial_current = saved_dev;
- bd->bi_baudrate = saved_baud;
+ gd->baudrate = saved_baud;
serial_reinit_all();
serial_setbrg();
if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
- setbits_be32(&ehci->control, UTMI_PHY_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_UTMI);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(&ehci->control, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ USB_EN);
} else {
- setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+ CONTROL_REGISTER_W1C_MASK, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
lcdc_writel(®s->lcdc_lcdcfg1, value);
- value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
- value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
+ value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
+ value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg2, value);
- value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
- value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
+ value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
+ value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg3, value);
/* Display size */
#include <common.h>
#include <asm/errno.h>
+#include <asm/global_data.h>
#include <linux/string.h>
#include <linux/list.h>
#include <linux/fb.h>
#include "mxcfb.h"
#include "ipu_regs.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
fbi->screen_size = fbi->fix.smem_len;
+ gd->fb_base = fbi->fix.smem_start;
+
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
restart:
fs->curr_blkno++;
/* get the blockbitmap index respective to blockno */
- if (fs->blksz != 1024) {
- bg_idx = fs->curr_blkno / blk_per_grp;
- } else {
- bg_idx = fs->curr_blkno / blk_per_grp;
+ bg_idx = fs->curr_blkno / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = fs->curr_blkno % blk_per_grp;
if (!remainder)
bg_idx--;
return blknr;
}
-void ext4fs_close(void)
+/**
+ * ext4fs_reinit_global() - Reinitialize values of ext4 write implementation's
+ * global pointers
+ *
+ * This function assures that for a file with the same name but different size
+ * the sequential store on the ext4 filesystem will be correct.
+ *
+ * In this function the global data, responsible for internal representation
+ * of the ext4 data are initialized to the reset state. Without this, during
+ * replacement of the smaller file with the bigger truncation of new file was
+ * performed.
+ */
+void ext4fs_reinit_global(void)
{
- if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
- ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
- ext4fs_file = NULL;
- }
- if (ext4fs_root != NULL) {
- free(ext4fs_root);
- ext4fs_root = NULL;
- }
if (ext4fs_indir1_block != NULL) {
free(ext4fs_indir1_block);
ext4fs_indir1_block = NULL;
ext4fs_indir3_blkno = -1;
}
}
+void ext4fs_close(void)
+{
+ if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
+ ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
+ ext4fs_file = NULL;
+ }
+ if (ext4fs_root != NULL) {
+ free(ext4fs_root);
+ ext4fs_root = NULL;
+ }
+
+ ext4fs_reinit_global();
+}
int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
struct ext2fs_node **fnode, int *ftype)
if (inode->b.blocks.indir_block != 0) {
debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
blknr = inode->b.blocks.indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
break;
debug("DICB releasing %u\n", *di_buffer);
- if (fs->blksz != 1024) {
- bg_idx = (*di_buffer) / blk_per_grp;
- } else {
- bg_idx = (*di_buffer) / blk_per_grp;
- remainder = (*di_buffer) % blk_per_grp;
+ bg_idx = *di_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *di_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
/* removing the parent double indirect block */
blknr = inode->b.blocks.double_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
for (j = 0; j < fs->blksz / sizeof(int); j++) {
if (*tip_buffer == 0)
break;
- if (fs->blksz != 1024) {
- bg_idx = (*tip_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tip_buffer) / blk_per_grp;
-
- remainder = (*tip_buffer) % blk_per_grp;
+ bg_idx = *tip_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *tip_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
* removing the grand parent blocks
* which is connected to inode
*/
- if (fs->blksz != 1024) {
- bg_idx = (*tigp_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tigp_buffer) / blk_per_grp;
-
- remainder = (*tigp_buffer) % blk_per_grp;
+ bg_idx = *tigp_buffer / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = *tigp_buffer % blk_per_grp;
if (!remainder)
bg_idx--;
}
/* removing the grand parent triple indirect block */
blknr = inode->b.blocks.triple_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
for (i = 0; i < no_blocks; i++) {
blknr = read_allocated_block(&(node_inode->inode), i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
no_blocks++;
for (i = 0; i < no_blocks; i++) {
blknr = read_allocated_block(&inode, i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
ext4fs_update();
ext4fs_deinit();
+ ext4fs_reinit_global();
if (ext4fs_init() != 0) {
printf("error in File System init\n");
__u32 ret = 0x00;
__u16 val1, val2;
+ if (CHECK_CLUST(entry, mydata->fatsize)) {
+ printf("Error: Invalid FAT entry: 0x%08x\n", entry);
+ return ret;
+ }
+
switch (mydata->fatsize) {
case 32:
bufnum = entry / FAT32BUFSIZE;
return dentptr;
}
+ /*
+ * In FAT16/12, the root dir is locate before data area, shows
+ * in following:
+ * -------------------------------------------------------------
+ * | Boot | FAT1 & 2 | Root dir | Data (start from cluster #2) |
+ * -------------------------------------------------------------
+ *
+ * As a result if curclust is in Root dir, it is a negative
+ * number or 0, 1.
+ *
+ */
+ if (mydata->fatsize != 32 && (int)curclust <= 1) {
+ /* Current clust is in root dir, set to next clust */
+ curclust++;
+ if ((int)curclust <= 1)
+ continue; /* continue to find */
+
+ /* Reach the end of root dir */
+ empty_dentptr = dentptr;
+ return NULL;
+ }
+
curclust = get_fatent_value(mydata, dir_curclust);
- if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) {
+ if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
empty_dentptr = dentptr;
return NULL;
}
}
mydata->fatbufnum = -1;
- mydata->fatbuf = malloc(FATBUFSIZE);
+ mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
return -1;
ubifs_msg("reserved for root: %llu bytes (%llu KiB)",
c->report_rp_size, c->report_rp_size >> 10);
- dbg_msg("compiled on: " __DATE__ " at " __TIME__);
dbg_msg("min. I/O unit size: %d bytes", c->min_io_size);
dbg_msg("LEB size: %d bytes (%d KiB)",
c->leb_size, c->leb_size >> 10);
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
int cpu_init_r (void);
#if defined(CONFIG_MPC8260)
#include <u-boot/crc.h>
/* lib/rand.c */
-#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
#define RAND_MAX -1U
void srand(unsigned int seed);
unsigned int rand(void);
unsigned int rand_r(unsigned int *seedp);
-#endif
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
#define CONFIG_LIB_RAND
#endif
+#if defined(CONFIG_API) && defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#endif
+
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* B4860 QDS board configuration file
*/
#define IDT_SERDES1_ADDRESS 0x6E
#define IDT_SERDES2_ADDRESS 0x6C
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM 0xa
+#define I2C_DPM_ADDR 0x28
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=b4860qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/* For emulation this causes u-boot to jump to the start of the proof point
app code automatically */
#endif
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
+#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
- /*
- * Config the L2 Cache as L2 SRAM
- */
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
+#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
+/*
+ * P1020 and it's derivatives support max 32bit DDR width
+ * So Reduce available DDR size
+*/
+#define CONFIG_SYS_SDRAM_SIZE 512
+#else
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
"fdtaddr=c00000\0" \
"fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t2080qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080qds/t2080qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080rdb/t2080rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240emu/t4240emu.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the proof point
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t4240qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240RDB
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#endif
+
+#define CONFIG_DDR_ECC
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x54
+#define SPD_EEPROM_ADDRESS3 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_CORTINA_FW_ADDR 0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR 0x10
+#define FM1_10GEC2_PHY_ADDR 0x11
+#define FM2_10GEC1_PHY_ADDR 0x12
+#define FM2_10GEC2_PHY_ADDR 0x13
+#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240rdb/t4240rdb.dtb\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+/* Secure Boot target was not getting build for T4240 because of
+ * increased binary size. So the size is being reduced by removing USB
+ * which is anyways not used in Secure Environment.
+ */
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_ROOTPATH "/romfs/brettl2"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
#endif
#define CONFIG_PHY_ADDR 3
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf526-ezbrd
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf527-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf537-pnav
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_ROOTPATH "/romfs"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME cm-bf527
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME cm-bf537e
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME cm-bf537u
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p4080ds/p4080ds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+
+#define CONFIG_LIB_RAND
#endif
/*
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_HZ 1000
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM 0x0
-/* enable protected RAM */
-#define CONFIG_PRAM 0
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page */
+#define CONFIG_KM_RESERVED_PRAM 0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
#define CONFIG_KM_CRAMFS_ADDR 0x2000000
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ERRATA
/* we don't need flash support */
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#endif
#endif
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_MMC
#ifdef CONFIG_MMC
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CROS_EC
#define CONFIG_CMD_CROS_EC
#define CONFIG_CROS_EC_SANDBOX
-#define CONFIG_KEYBOARD
-#define CONFIG_CROS_EC_KEYB
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SOUND_SANDBOX
#define CONFIG_CMD_SOUND
+#ifndef SANDBOX_NO_SDL
#define CONFIG_SANDBOX_SDL
+#endif
+
+/* LCD and keyboard require SDL support */
+#ifdef CONFIG_SANDBOX_SDL
#define CONFIG_LCD
#define CONFIG_VIDEO_SANDBOX_SDL
#define CONFIG_CMD_BMP
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define LCD_BPP LCD_COLOR16
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_KEYBOARD
+
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+#endif
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
#ifndef __T4QDS_H
#define __T4QDS_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#define CONFIG_HOSTNAME tcm-bf518
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
#define CONFIG_HOSTNAME tcm-bf537
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
int ext4fs_read(char *buf, unsigned len);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
+void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
int ext4fs_exists(const char *filename);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
+#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff8 : 0xfff8) : \
+ 0xffffff8))
#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
- (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
+ (x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff0 : 0xfff0) : \
+ 0xffffff0))
typedef struct boot_sector {
__u8 ignored[3]; /* Bootstrap code */
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
-#ifdef CONFIG_RANDOM_MACADDR
-/*
- * The u-boot policy does not allow hardcoded ethernet addresses. Under the
- * following circumstances a random generated address is allowed:
- * - in emergency cases, where you need a working network connection to set
- * the ethernet address.
- * Eg. you want a rescue boot and don't have a serial port to access the
- * CLI to set environment variables.
- *
- * In these cases, we generate a random locally administered ethernet address.
- *
- * Args:
- * enetaddr - returns 6 byte hardware address
- */
-extern void eth_random_enetaddr(uchar *enetaddr);
-#endif
-
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(void *packet, int length); /* Send a packet */
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}
+/**
+ * eth_random_addr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void eth_random_addr(uchar *addr)
+{
+ int i;
+ unsigned int seed = get_timer(0);
+
+ for (i = 0; i < 6; i++)
+ addr[i] = rand_r(&seed);
+
+ addr[0] &= 0xfe; /* clear multicast bit */
+ addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+}
+
/* Convert an IP address to a string */
extern void ip_to_string(IPaddr_t x, char *s);
#define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
#define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08
#include <xilinx.h>
-extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan2_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan2_op;
/* Device Image Sizes
*********************************************************************/
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
#endif /* _SPARTAN2_H_ */
#include <xilinx.h>
-extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan3_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan3_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan3_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
- Xilinx_bwr_fn bwr; /* block write function */
- Xilinx_abort_fn abort;
-} Xilinx_Spartan3_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+ xilinx_bwr_fn bwr; /* block write function */
+ xilinx_abort_fn abort;
+} xilinx_spartan3_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan3_op;
/* Device Image Sizes
*********************************************************************/
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
#endif /* _SPARTAN3_H_ */
#include <asm/processor.h>
+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
#include <xilinx.h>
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op virtex2_op;
/*
* Slave SelectMap Implementation function table.
*/
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+} xilinx_virtex2_slave_serial_fns;
/* Device Image Sizes (in bytes)
*********************************************************************/
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
#endif /* _VIRTEX2_H_ */
/* Xilinx types
*********************************************************************/
-typedef enum { /* typedef Xilinx_iface */
+typedef enum { /* typedef xilinx_iface */
min_xilinx_iface_type, /* low range check value */
slave_serial, /* serial data and external clock */
master_serial, /* serial data w/ internal clock (not used) */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
max_xilinx_iface_type /* insert all new types before this */
-} Xilinx_iface; /* end, typedef Xilinx_iface */
+} xilinx_iface; /* end, typedef xilinx_iface */
-typedef enum { /* typedef Xilinx_Family */
+typedef enum { /* typedef xilinx_family */
min_xilinx_type, /* low range check value */
- Xilinx_Spartan2, /* Spartan-II Family */
- Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
- Xilinx_Spartan3, /* Spartan-III Family */
+ xilinx_spartan2, /* Spartan-II Family */
+ xilinx_virtexE, /* Virtex-E Family */
+ xilinx_virtex2, /* Virtex2 Family */
+ xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
max_xilinx_type /* insert all new types before this */
-} Xilinx_Family; /* end, typedef Xilinx_Family */
+} xilinx_family; /* end, typedef xilinx_family */
-typedef struct { /* typedef Xilinx_desc */
- Xilinx_Family family; /* part type */
- Xilinx_iface iface; /* interface type */
+typedef struct { /* typedef xilinx_desc */
+ xilinx_family family; /* part type */
+ xilinx_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
+ struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
-} Xilinx_desc; /* end, typedef Xilinx_desc */
+} xilinx_desc; /* end, typedef xilinx_desc */
+
+struct xilinx_fpga_op {
+ int (*load)(xilinx_desc *, const void *, size_t);
+ int (*dump)(xilinx_desc *, const void *, size_t);
+ int (*info)(xilinx_desc *);
+};
/* Generic Xilinx Functions
*********************************************************************/
-extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int xilinx_info(Xilinx_desc *desc);
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+int xilinx_info(xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
-typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
-typedef int (*Xilinx_init_fn)( int cookie );
-typedef int (*Xilinx_err_fn)( int cookie );
-typedef int (*Xilinx_done_fn)( int cookie );
-typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
-typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
-typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
-typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
-typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
-typedef int (*Xilinx_busy_fn)( int cookie );
-typedef int (*Xilinx_abort_fn)( int cookie );
-typedef int (*Xilinx_pre_fn)( int cookie );
-typedef int (*Xilinx_post_fn)( int cookie );
-typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
+typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
+typedef int (*xilinx_init_fn)(int cookie);
+typedef int (*xilinx_err_fn)(int cookie);
+typedef int (*xilinx_done_fn)(int cookie);
+typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
+typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
+typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
+typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
+typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
+typedef int (*xilinx_busy_fn)(int cookie);
+typedef int (*xilinx_abort_fn)(int cookie);
+typedef int (*xilinx_pre_fn)(int cookie);
+typedef int (*xilinx_post_fn)(int cookie);
+typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
#endif /* _XILINX_H_ */
#include <xilinx.h>
-extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int zynq_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op zynq_op;
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
#endif /* _ZYNQPL_H_ */
#ifndef USE_HOSTCC
#include <common.h>
+#include <linux/string.h>
+#else
+#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include <linux/string.h>
#include <sha256.h>
/*
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- uint plat_ratio, bus_clk, sys_clk = 0;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- uint val, temp, sysclk_mask;
-
- val = pgpio->gpdat;
- sysclk_mask = val & SYSCLK_MASK;
- temp = val & BOARDREV_MASK;
- if (temp == BOARDREV_C) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_100;
- } else if (temp == BOARDREV_B) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_50;
- }
-
- plat_ratio = gur->porpllsr & 0x0000003e;
- plat_ratio >>= 1;
- bus_clk = plat_ratio * sys_clk;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to DDR and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
return ((skip_state = getenv(enetvar)) != NULL);
}
-#ifdef CONFIG_RANDOM_MACADDR
-void eth_random_enetaddr(uchar *enetaddr)
-{
- uint32_t rval;
-
- srand(get_timer(0));
-
- rval = rand();
- enetaddr[0] = rval & 0xff;
- enetaddr[1] = (rval >> 8) & 0xff;
- enetaddr[2] = (rval >> 16) & 0xff;
-
- rval = rand();
- enetaddr[3] = rval & 0xff;
- enetaddr[4] = (rval >> 8) & 0xff;
- enetaddr[5] = (rval >> 16) & 0xff;
-
- /* make sure it's local and unicast */
- enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01;
-}
-#endif
-
/*
* CPU and board-specific Ethernet initializations. Aliased function
* signals caller to move on
ifdef SOC
libs-y += $(CPUDIR)/$(SOC)/
endif
-libs-y += board/$(BOARDDIR)/
+libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
--- /dev/null
+#include "../../lib/aes.c"
A sign-off is added automatically to your patches (this is
probably a bug). If you put this tag in your patches, it will
override the default signoff that patman automatically adds.
+ Multiple duplicate signoffs will be removed.
Tested-by: Their Name <email>
Reviewed-by: Their Name <email>
self.tags = []
self.changes = {}
self.cc_list = []
+ self.signoff_set = set()
self.notes = []
def AddChange(self, version, info):
cc_list: List of aliases or email addresses
"""
self.cc_list += cc_list
+
+ def CheckDuplicateSignoff(self, signoff):
+ """Check a list of signoffs we have send for this patch
+
+ Args:
+ signoff: Signoff line
+ Returns:
+ True if this signoff is new, False if we have already seen it.
+ """
+ if signoff in self.signoff_set:
+ return False
+ self.signoff_set.add(signoff)
+ return True
import sys
import terminal
+import checkpatch
import settings
Args:
fname: filename of patch file to apply
"""
+ col = terminal.Color()
cmd = ['git', 'am', fname]
pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE,
stderr=subprocess.PIPE)
print line
match = re_error.match(line)
if match:
- print GetWarningMsg('warning', match.group(1), int(match.group(2)),
- 'Patch failed')
+ print checkpatch.GetWarningMsg(col, 'warning', match.group(1),
+ int(match.group(2)), 'Patch failed')
return pipe.returncode == 0, stdout
def ApplyPatches(verbose, args, start_point):
re_allowed_after_test = re.compile('^Signed-off-by:')
# Signoffs
-re_signoff = re.compile('^Signed-off-by:')
+re_signoff = re.compile('^Signed-off-by: *(.*)')
# The start of the cover letter
re_cover = re.compile('^Cover-letter:')
commit_tag_match = re_commit_tag.match(line)
commit_match = re_commit.match(line) if self.is_log else None
cover_cc_match = re_cover_cc.match(line)
+ signoff_match = re_signoff.match(line)
tag_match = None
if self.state == STATE_PATCH_HEADER:
tag_match = re_tag.match(line)
if is_blank:
# Blank line ends this change list
self.in_change = 0
- elif line == '---' or re_signoff.match(line):
+ elif line == '---':
self.in_change = 0
out = self.ProcessLine(line)
else:
else:
self.tags.append(line);
+ # Suppress duplicate signoffs
+ elif signoff_match:
+ if (self.is_log or
+ self.commit.CheckDuplicateSignoff(signoff_match.group(1))):
+ out = [line]
+
# Well that means this is an ordinary line
else:
pos = 1
projects / karo-tx-uboot.git / commitdiff
