Merge branch 'master' of git://git.denx.de/u-boot-arm
authorMinkyu Kang <mk7.kang@samsung.com>
Fri, 30 Oct 2009 03:14:40 +0000 (12:14 +0900)
committerMinkyu Kang <mk7.kang@samsung.com>
Fri, 30 Oct 2009 03:14:40 +0000 (12:14 +0900)
Conflicts:

board/eukrea/cpu9260/cpu9260.c
drivers/serial/serial_s5pc1xx.c
include/asm-arm/arch-s5pc1xx/clock.h
include/asm-arm/arch-s5pc1xx/gpio.h
include/asm-arm/arch-s5pc1xx/pwm.h
include/asm-arm/arch-s5pc1xx/uart.h
include/configs/cpu9260.h
include/configs/cpuat91.h
include/configs/davinci_dm355evm.h
include/linux/mtd/samsung_onenand.h

514 files changed:
MAINTAINERS
MAKEALL
Makefile
board/LEOX/elpt860/u-boot.lds
board/LEOX/elpt860/u-boot.lds.debug
board/MAI/AmigaOneG3SE/u-boot.lds
board/Marvell/db64360/u-boot.lds
board/Marvell/db64460/u-boot.lds
board/RPXClassic/u-boot.lds
board/RPXClassic/u-boot.lds.debug
board/RPXlite/u-boot.lds
board/RPXlite/u-boot.lds.debug
board/RPXlite_dw/u-boot.lds
board/RPXlite_dw/u-boot.lds.debug
board/RRvision/u-boot.lds
board/adder/u-boot.lds
board/altera/ep1c20/ep1c20.c
board/altera/ep1s10/ep1s10.c
board/altera/ep1s40/ep1s40.c
board/amcc/acadia/u-boot-nand.lds
board/amcc/acadia/u-boot.lds
board/amcc/bamboo/bamboo.c
board/amcc/bamboo/u-boot-nand.lds
board/amcc/bamboo/u-boot.lds
board/amcc/bubinga/u-boot.lds
board/amcc/canyonlands/canyonlands.c
board/amcc/canyonlands/u-boot-nand.lds
board/amcc/canyonlands/u-boot.lds
board/amcc/ebony/ebony.c
board/amcc/ebony/u-boot.lds
board/amcc/katmai/katmai.c
board/amcc/katmai/u-boot.lds
board/amcc/kilauea/kilauea.c
board/amcc/kilauea/u-boot-nand.lds
board/amcc/kilauea/u-boot.lds
board/amcc/luan/epld.h
board/amcc/luan/luan.c
board/amcc/luan/u-boot.lds
board/amcc/makalu/makalu.c
board/amcc/makalu/u-boot.lds
board/amcc/ocotea/ocotea.c
board/amcc/ocotea/u-boot.lds
board/amcc/redwood/u-boot.lds
board/amcc/sequoia/sequoia.c
board/amcc/sequoia/u-boot-nand.lds
board/amcc/sequoia/u-boot-ram.lds
board/amcc/sequoia/u-boot.lds
board/amcc/taihu/u-boot.lds
board/amcc/taishan/showinfo.c
board/amcc/taishan/taishan.c
board/amcc/taishan/u-boot.lds
board/amcc/walnut/u-boot.lds
board/amcc/yosemite/u-boot.lds
board/amcc/yosemite/yosemite.c
board/amcc/yucca/u-boot.lds
board/amcc/yucca/yucca.c
board/amirix/ap1000/u-boot.lds
board/armltd/integrator/integrator.c
board/armltd/versatile/versatile.c
board/bf533-ezkit/bf533-ezkit.c
board/bf533-stamp/bf533-stamp.c
board/bf538f-ezkit/bf538f-ezkit.c
board/bf561-ezkit/bf561-ezkit.c
board/blackstamp/blackstamp.c
board/c2mon/u-boot.lds
board/c2mon/u-boot.lds.debug
board/cerf250/cerf250.c
board/cm-bf533/cm-bf533.c
board/cm-bf561/cm-bf561.c
board/cm5200/u-boot.lds
board/cogent/u-boot.lds
board/cogent/u-boot.lds.debug
board/cradle/cradle.c
board/cray/L1/u-boot.lds
board/cray/L1/u-boot.lds.debug
board/csb272/u-boot.lds
board/csb472/u-boot.lds
board/dave/PPChameleonEVB/u-boot.lds
board/davinci/dm355evm/dm355evm.c
board/davinci/dm355leopard/Makefile [new file with mode: 0644]
board/davinci/dm355leopard/config.mk [new file with mode: 0644]
board/davinci/dm355leopard/dm355leopard.c [new file with mode: 0644]
board/davinci/dm365evm/dm365evm.c
board/davinci/dm6467evm/Makefile [new file with mode: 0644]
board/davinci/dm6467evm/config.mk [new file with mode: 0644]
board/davinci/dm6467evm/dm6467evm.c [new file with mode: 0644]
board/delta/delta.c
board/digsy_mtc/cmd_mtc.c
board/digsy_mtc/digsy_mtc.c
board/dnp1110/dnp1110.c
board/eltec/bab7xx/u-boot.lds
board/eltec/elppc/u-boot.lds
board/eltec/mhpc/u-boot.lds
board/eltec/mhpc/u-boot.lds.debug
board/emk/top860/u-boot.lds
board/emk/top860/u-boot.lds.debug
board/ep88x/u-boot.lds
board/eric/u-boot.lds
board/esd/adciop/u-boot.lds
board/esd/apc405/u-boot.lds
board/esd/ar405/u-boot.lds
board/esd/ash405/u-boot.lds
board/esd/canbt/u-boot.lds
board/esd/cms700/u-boot.lds
board/esd/common/cmd_loadpci.c
board/esd/cpci2dp/u-boot.lds
board/esd/cpci405/u-boot.lds
board/esd/cpci750/u-boot.lds
board/esd/cpciiser4/u-boot.lds
board/esd/dasa_sim/u-boot.lds
board/esd/dp405/u-boot.lds
board/esd/du405/u-boot.lds
board/esd/du440/du440.c
board/esd/du440/u-boot.lds
board/esd/hh405/u-boot.lds
board/esd/hub405/u-boot.lds
board/esd/ocrtc/u-boot.lds
board/esd/pci405/u-boot.lds
board/esd/plu405/u-boot.lds
board/esd/pmc405/u-boot.lds
board/esd/pmc405de/u-boot.lds
board/esd/pmc440/cmd_pmc440.c
board/esd/pmc440/fpga.c
board/esd/pmc440/init.S
board/esd/pmc440/pmc440.c
board/esd/pmc440/sdram.c
board/esd/pmc440/u-boot-nand.lds
board/esd/pmc440/u-boot.lds
board/esd/voh405/u-boot.lds
board/esd/vom405/u-boot.lds
board/esd/wuh405/u-boot.lds
board/esteem192e/u-boot.lds
board/etx094/u-boot.lds
board/etx094/u-boot.lds.debug
board/eukrea/cpu9260/cpu9260.c
board/evb64260/u-boot.lds
board/exbitgen/init.S
board/exbitgen/u-boot.lds
board/fads/u-boot.lds
board/fads/u-boot.lds.debug
board/flagadm/u-boot.lds
board/flagadm/u-boot.lds.debug
board/freescale/mpc5121ads/mpc5121ads.c
board/freescale/mpc7448hpc2/u-boot.lds
board/freescale/mpc8548cds/mpc8548cds.c
board/freescale/mpc8610hpcd/u-boot.lds
board/freescale/mpc8641hpcn/u-boot.lds
board/g2000/u-boot.lds
board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
board/gaisler/gr_ep2s60/gr_ep2s60.c
board/gdsys/dlvision/u-boot.lds
board/gdsys/gdppc440etx/gdppc440etx.c
board/gdsys/gdppc440etx/u-boot.lds
board/gdsys/intip/intip.c
board/gdsys/intip/u-boot.lds
board/gdsys/neo/u-boot.lds
board/gen860t/fpga.c
board/gen860t/u-boot-flashenv.lds
board/gen860t/u-boot.lds
board/genietv/u-boot.lds
board/genietv/u-boot.lds.debug
board/gth/u-boot.lds
board/hermes/u-boot.lds
board/hermes/u-boot.lds.debug
board/hymod/u-boot.lds
board/hymod/u-boot.lds.debug
board/icu862/u-boot.lds
board/icu862/u-boot.lds.debug
board/inka4x0/inka4x0.c
board/inka4x0/inkadiag.c
board/innokom/innokom.c
board/ip860/u-boot.lds
board/ip860/u-boot.lds.debug
board/ivm/u-boot.lds
board/ivm/u-boot.lds.debug
board/jse/u-boot.lds
board/keymile/km8xx/u-boot.lds
board/korat/korat.c
board/korat/u-boot-F7FC.lds
board/korat/u-boot.lds
board/kup/kup4k/u-boot.lds
board/kup/kup4k/u-boot.lds.debug
board/kup/kup4x/u-boot.lds
board/kup/kup4x/u-boot.lds.debug
board/lantec/u-boot.lds
board/lantec/u-boot.lds.debug
board/logicpd/zoom2/zoom2.c
board/logodl/logodl.c
board/lpd7a40x/lpd7a40x.c
board/lwmon/u-boot.lds
board/lwmon/u-boot.lds.debug
board/lwmon5/lwmon5.c
board/lwmon5/u-boot.lds
board/matrix_vision/mvbc_p/fpga.c
board/matrix_vision/mvblm7/fpga.c
board/mbx8xx/u-boot.lds
board/mbx8xx/u-boot.lds.debug
board/ml2/u-boot.lds
board/ml2/u-boot.lds.debug
board/mousse/u-boot.lds
board/mousse/u-boot.lds.rom
board/mpl/common/memtst.c
board/mpl/common/pci.c
board/mpl/mip405/mip405.c
board/mpl/mip405/u-boot.lds
board/mpl/pati/pati.c
board/mpl/pip405/u-boot.lds
board/mpl/pip405/u-boot.lds.debug
board/mpl/vcma9/vcma9.c
board/ms7722se/ms7722se.c
board/munices/u-boot.lds
board/nc650/u-boot.lds
board/nc650/u-boot.lds.debug
board/netphone/u-boot.lds
board/netphone/u-boot.lds.debug
board/netstal/hcu4/u-boot.lds
board/netstal/hcu5/hcu5.c
board/netstal/hcu5/u-boot.lds
board/netstal/mcu25/u-boot.lds
board/netstar/eeprom.c
board/netstar/netstar.c
board/netta/u-boot.lds
board/netta/u-boot.lds.debug
board/netta2/u-boot.lds
board/netta2/u-boot.lds.debug
board/netvia/u-boot.lds
board/netvia/u-boot.lds.debug
board/nx823/u-boot.lds
board/nx823/u-boot.lds.debug
board/pcippc2/u-boot.lds
board/pcs440ep/pcs440ep.c
board/pcs440ep/u-boot.lds
board/ppmc7xx/u-boot.lds
board/prodrive/alpr/alpr.c
board/prodrive/alpr/fpga.c
board/prodrive/alpr/u-boot.lds
board/prodrive/p3mx/p3mx.c
board/prodrive/p3mx/u-boot.lds
board/prodrive/p3p440/p3p440.c
board/prodrive/p3p440/u-boot.lds
board/psyent/pk1c20/pk1c20.c
board/pxa255_idp/pxa_idp.c
board/quad100hd/u-boot.lds
board/quantum/u-boot.lds
board/quantum/u-boot.lds.debug
board/r360mpi/u-boot.lds
board/rbc823/u-boot.lds
board/renesas/MigoR/migo_r.c
board/rmu/u-boot.lds
board/rmu/u-boot.lds.debug
board/rsdproto/u-boot.lds
board/sandburst/common/ppc440gx_i2c.h
board/sandburst/common/sb_common.c
board/sandburst/karef/u-boot.lds
board/sandburst/karef/u-boot.lds.debug
board/sandburst/metrobox/u-boot.lds
board/sandburst/metrobox/u-boot.lds.debug
board/sbc405/u-boot.lds
board/sbc8641d/u-boot.lds
board/sc3/u-boot.lds
board/siemens/CCM/u-boot.lds
board/siemens/CCM/u-boot.lds.debug
board/siemens/IAD210/u-boot.lds
board/siemens/pcu_e/u-boot.lds
board/siemens/pcu_e/u-boot.lds.debug
board/sixnet/u-boot.lds
board/snmc/qs850/u-boot.lds
board/snmc/qs860t/u-boot.lds
board/spc1920/u-boot.lds
board/spd8xx/u-boot.lds
board/spd8xx/u-boot.lds.debug
board/st/nhk8815/nhk8815.c
board/stx/stxxtc/u-boot.lds
board/stx/stxxtc/u-boot.lds.debug
board/svm_sc8xx/u-boot.lds
board/svm_sc8xx/u-boot.lds.debug
board/ti/sdp3430/Makefile [new file with mode: 0644]
board/ti/sdp3430/config.mk [new file with mode: 0644]
board/ti/sdp3430/sdp.c [new file with mode: 0644]
board/ti/sdp3430/sdp.h [new file with mode: 0644]
board/tqc/tqm5200/tqm5200.c
board/tqc/tqm8xx/u-boot.lds
board/tqc/tqm8xx/u-boot.lds.debug
board/uc100/u-boot.lds
board/uc100/u-boot.lds.debug
board/v37/u-boot.lds
board/voiceblue/eeprom.c
board/voiceblue/voiceblue.c
board/w7o/u-boot.lds
board/w7o/u-boot.lds.debug
board/westel/amx860/u-boot.lds
board/westel/amx860/u-boot.lds.debug
board/xaeniax/xaeniax.c
board/xes/xpedite1000/u-boot.lds
board/xes/xpedite1000/u-boot.lds.debug
board/xes/xpedite1000/xpedite1000.c
board/xes/xpedite5170/config.mk
board/xes/xpedite5200/config.mk
board/xes/xpedite5370/config.mk
board/xilinx/ml300/u-boot.lds
board/xilinx/ml300/u-boot.lds.debug
board/xilinx/ppc405-generic/u-boot-ram.lds
board/xilinx/ppc405-generic/u-boot-rom.lds
board/xilinx/ppc440-generic/u-boot-ram.lds
board/xilinx/ppc440-generic/u-boot-rom.lds
board/xm250/xm250.c
board/xsengine/xsengine.c
board/zeus/u-boot.lds
board/zylonite/zylonite.c
common/cmd_bootm.c
common/cmd_date.c
common/cmd_reginfo.c
common/dlmalloc.c
common/env_common.c
common/hush.c
common/image.c
common/serial.c
common/stdio.c
cpu/74xx_7xx/start.S
cpu/arm926ejs/start.S
cpu/arm_cortexa8/omap3/mem.c
cpu/arm_cortexa8/omap3/sys_info.c
cpu/mpc512x/fixed_sdram.c
cpu/mpc512x/start.S
cpu/mpc512x/u-boot.lds
cpu/mpc5xx/start.S
cpu/mpc5xx/u-boot.lds
cpu/mpc5xxx/start.S
cpu/mpc5xxx/u-boot-customlayout.lds
cpu/mpc5xxx/u-boot.lds
cpu/mpc8220/start.S
cpu/mpc8220/u-boot.lds
cpu/mpc824x/start.S
cpu/mpc824x/u-boot.lds
cpu/mpc8260/start.S
cpu/mpc8260/u-boot.lds
cpu/mpc83xx/start.S
cpu/mpc83xx/u-boot.lds
cpu/mpc85xx/start.S
cpu/mpc85xx/u-boot.lds
cpu/mpc86xx/start.S
cpu/mpc8xx/start.S
cpu/ppc4xx/44x_spd_ddr2.c
cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
cpu/ppc4xx/4xx_pci.c
cpu/ppc4xx/4xx_pcie.c
cpu/ppc4xx/Makefile
cpu/ppc4xx/cpu.c
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/denali_spd_ddr2.c
cpu/ppc4xx/ecc.c
cpu/ppc4xx/ecc.h
cpu/ppc4xx/miiphy.c
cpu/ppc4xx/reginfo.c [new file with mode: 0644]
cpu/ppc4xx/speed.c
cpu/ppc4xx/start.S
disk/part.c
doc/README.bitbangMII [new file with mode: 0644]
doc/README.drivers.eth [new file with mode: 0644]
drivers/bios_emulator/x86emu/ops.c
drivers/bios_emulator/x86emu/ops2.c
drivers/fpga/ACEX1K.c
drivers/fpga/altera.c
drivers/fpga/cyclon2.c
drivers/fpga/fpga.c
drivers/fpga/spartan2.c
drivers/fpga/spartan3.c
drivers/fpga/stratixII.c
drivers/fpga/virtex2.c
drivers/fpga/xilinx.c
drivers/mtd/nand/nand.c
drivers/net/4xx_enet.c
drivers/net/Makefile
drivers/net/kirkwood_egiga.c
drivers/net/phy/miiphybb.c
drivers/net/phy/mv88e61xx.c
drivers/net/smc91111.c
drivers/net/smc91111.h
drivers/net/smc911x.c
drivers/net/tsec.c
drivers/serial/serial_s5pc1xx.c
examples/standalone/smc91111_eeprom.c
fs/ubifs/ubifs.c
include/4xx_i2c.h
include/ACEX1K.h
include/altera.h
include/asm-arm/arch-davinci/hardware.h
include/asm-arm/arch-omap3/sys_proto.h
include/asm-arm/arch-s5pc1xx/clock.h
include/asm-arm/arch-s5pc1xx/gpio.h
include/asm-arm/arch-s5pc1xx/pwm.h
include/asm-arm/arch-s5pc1xx/uart.h
include/asm-arm/config.h
include/asm-arm/global_data.h
include/asm-microblaze/config.h
include/asm-microblaze/global_data.h
include/asm-nios/config.h
include/asm-nios/global_data.h
include/asm-nios2/config.h
include/asm-nios2/global_data.h
include/asm-ppc/config.h
include/asm-ppc/global_data.h
include/asm-ppc/immap_512x.h
include/asm-ppc/mpc512x.h
include/asm-ppc/ppc4xx-sdram.h
include/asm-ppc/processor.h
include/asm-sh/config.h
include/asm-sh/global_data.h
include/configs/EP1C20.h
include/configs/EP1S10.h
include/configs/EP1S40.h
include/configs/ISPAN.h
include/configs/MPC8260ADS.h
include/configs/MPC8266ADS.h
include/configs/MPC8560ADS.h
include/configs/MigoR.h
include/configs/PK1C20.h
include/configs/PMC440.h
include/configs/Rattler.h
include/configs/SBC8540.h
include/configs/TQM5200.h
include/configs/TQM8272.h
include/configs/VoVPN-GW.h
include/configs/XPEDITE5170.h
include/configs/XPEDITE5200.h
include/configs/XPEDITE5370.h
include/configs/ZPC1900.h
include/configs/bf533-ezkit.h
include/configs/bf533-stamp.h
include/configs/bf538f-ezkit.h
include/configs/bf561-ezkit.h
include/configs/bfin_adi_common.h
include/configs/blackstamp.h
include/configs/cerf250.h
include/configs/cm-bf533.h
include/configs/cm-bf561.h
include/configs/cpu9260.h
include/configs/cpuat91.h
include/configs/cradle.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h [new file with mode: 0644]
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467evm.h [new file with mode: 0644]
include/configs/davinci_dvevm.h
include/configs/davinci_sonata.h
include/configs/devkit8000.h
include/configs/dnp1110.h
include/configs/ep8248.h
include/configs/ep82xxm.h
include/configs/gr_cpci_ax2000.h
include/configs/gr_ep2s60.h
include/configs/gw8260.h
include/configs/hymod.h
include/configs/inka4x0.h
include/configs/innokom.h
include/configs/integratorcp.h
include/configs/logodl.h
include/configs/lpd7a400-10.h
include/configs/lpd7a404-10.h
include/configs/ms7722se.h
include/configs/muas3001.h
include/configs/netstar.h
include/configs/nhk8815.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_overo.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h [new file with mode: 0644]
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/p3mx.h
include/configs/ppmc8260.h
include/configs/pxa255_idp.h
include/configs/sacsng.h
include/configs/sbc8260.h
include/configs/sbc8560.h
include/configs/versatile.h
include/configs/voiceblue.h
include/configs/xaeniax.h
include/configs/xm250.h
include/configs/xsengine.h
include/configs/zylonite.h
include/exports.h
include/fpga.h
include/linux/mtd/samsung_onenand.h
include/miiphy.h
include/net.h
include/netdev.h
include/post.h
include/ppc405.h
include/ppc440.h
include/ppc4xx.h
include/ppc4xx_enet.h
include/spartan2.h
include/spartan3.h
include/stratixII.h
include/virtex2.h
include/xilinx.h
lib_arm/board.c
lib_avr32/board.c
lib_blackfin/board.c
lib_i386/board.c
lib_m68k/board.c
lib_mips/board.c
lib_ppc/Makefile
lib_ppc/board.c
lib_ppc/config.mk
lib_ppc/extable.c
lib_sh/board.c
lib_sparc/board.c
post/board/lwmon/sysmon.c
post/board/lwmon5/sysmon.c
post/cpu/ppc4xx/ether.c
post/post.c

index 1bb2521..d70a9d2 100644 (file)
@@ -612,6 +612,13 @@ Sergey Kubushyn <ksi@koi8.net>
        SONATA          ARM926EJS
        SCHMOOGIE       ARM926EJS
 
+Sandeep Paulraj <s-paulraj@ti.com>
+
+       davinci_dm355evm        ARM926EJS
+       davinci_dm355leopard    ARM926EJS
+       davinci_dm365evm        ARM926EJS
+       davinci_dm6467evm       ARM926EJS
+
 Prakash Kumar <prakash@embedx.com>
 
        cerf250         xscale
@@ -628,6 +635,7 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 
 Nishanth Menon <nm@ti.com>
 
+       omap3_sdp3430   ARM CORTEX-A8 (OMAP3xx SoC)
        omap3_zoom1     ARM CORTEX-A8 (OMAP3xx SoC)
 
 David Müller <d.mueller@elsoft.ch>
diff --git a/MAKEALL b/MAKEALL
index 6122e9f..5492d8f 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -567,6 +567,8 @@ LIST_ARM9="                 \
        davinci_sffsdr          \
        davinci_sonata          \
        davinci_dm355evm        \
+       davinci_dm355leopard    \
+       davinci_dm6467evm       \
 "
 
 #########################################################################
@@ -603,6 +605,7 @@ LIST_ARM_CORTEX_A8="                \
        omap3_overo             \
        omap3_evm               \
        omap3_pandora           \
+       omap3_sdp3430           \
        omap3_zoom1             \
        omap3_zoom2             \
        smdkc100                \
index 1df7e9d..b91b1c0 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2927,9 +2927,15 @@ davinci_sonata_config :  unconfig
 davinci_dm355evm_config :      unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
 
+davinci_dm355leopard_config :  unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355leopard davinci davinci
+
 davinci_dm365evm_config :      unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci
 
+davinci_dm6467evm_config :     unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+
 imx27lite_config:      unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
 
@@ -3138,6 +3144,9 @@ omap3_evm_config :        unconfig
 omap3_pandora_config : unconfig
        @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
 
+omap3_sdp3430_config : unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
+
 omap3_zoom1_config :   unconfig
        @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3
 
index c6b1f94..3c44b3e 100644 (file)
@@ -80,7 +80,6 @@ SECTIONS
     common/env_embedded.o              (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 434c9b7..5126083 100644 (file)
@@ -73,7 +73,6 @@ SECTIONS
     common/env_embedded.o      (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 66440da..18510a8 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index faa1c6c..47247ec 100644 (file)
@@ -67,7 +67,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ea85389..a2d940f 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index faa1c6c..47247ec 100644 (file)
@@ -67,7 +67,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ea85389..a2d940f 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7b7b83b..7ae7be0 100644 (file)
@@ -67,7 +67,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0f6ae69..83fdc15 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 17e6fa0..f22b25f 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     common/env_embedded.o      (.ppcenv)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 186dfe6..397ee2f 100644 (file)
@@ -54,7 +54,6 @@ SECTIONS
   {
     cpu/mpc8xx/start.o (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
     . = ALIGN(16);
     *(.eh_frame)
index c5bfb85..82900f7 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 int board_early_init_f (void)
 {
@@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
 {
        return (0);
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index de9bf42..cf886da 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 int board_early_init_f (void)
 {
@@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
 {
        return (0);
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index c0eca17..6395de7 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 int checkboard (void)
 {
@@ -33,3 +34,14 @@ phys_size_t initdram (int board_type)
 {
        return (0);
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index b769e94..738caa0 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x10000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b7aa160..d37200d 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 38186a5..2598f2c 100644 (file)
@@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index b769e94..738caa0 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x10000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 997d844..bcde534 100644 (file)
@@ -70,7 +70,6 @@ SECTIONS
     board/amcc/bamboo/bamboo.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b7aa160..d37200d 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index f359d23..91fae19 100644 (file)
@@ -28,6 +28,7 @@
 #include <asm/mmu.h>
 #include <asm/4xx_pcie.h>
 #include <asm/gpio.h>
+#include <asm/errno.h>
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
@@ -338,27 +339,27 @@ void pci_target_init(struct pci_controller * hose )
        /*
         * Disable everything
         */
-       out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
        /*
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         */
-       out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIX0_PIM0LAH, 0);
-       out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIX0_BAR0, 0);
+       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out_le32((void *)PCIL0_PIM0LAH, 0);
+       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out_le32((void *)PCIL0_BAR0, 0);
 
        /*
         * Program the board's subsystem id/vendor id
         */
-       out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -414,6 +415,8 @@ void pcie_setup_hoses(int busno)
                        ret = ppc4xx_init_pcie_endport(i);
                else
                        ret = ppc4xx_init_pcie_rootport(i);
+               if (ret == -ENODEV)
+                       continue;
                if (ret) {
                        printf("PCIE%d: initialization as %s failed\n", i,
                               is_end_point(i) ? "endpoint" : "root-complex");
index d18c536..47c6bd9 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x80000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b768532..22fb8b8 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/canyonlands/init.o      (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index e61b5de..0ca1acc 100644 (file)
@@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0SA, 0);        /* disable */
-       out32r(PCIX0_PIM1SA, 0);        /* disable */
-       out32r(PCIX0_PIM2SA, 0);        /* disable */
-       out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
+       out32r(PCIL0_PIM0SA, 0);        /* disable */
+       out32r(PCIL0_PIM1SA, 0);        /* disable */
+       out32r(PCIL0_PIM2SA, 0);        /* disable */
+       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
      * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIX0_PIM0LAH, 0);
-       out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out32r(PCIL0_PIM0LAH, 0);
+       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-       out32r(PCIX0_BAR0, 0);
+       out32r(PCIL0_BAR0, 0);
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index d569a14..4cb2e6c 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/ebony/init.o    (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index bcef707..908f1a5 100644 (file)
@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/4xx_pcie.h>
+#include <asm/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -304,27 +305,27 @@ void pci_target_init(struct pci_controller * hose )
        /*-------------------------------------------------------------------+
         * Disable everything
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*-------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*-------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -391,6 +392,8 @@ void pcie_setup_hoses(int busno)
                        ret = ppc4xx_init_pcie_endport(i);
                else
                        ret = ppc4xx_init_pcie_rootport(i);
+               if (ret == -ENODEV)
+                       continue;
                if (ret) {
                        printf("PCIE%d: initialization as %s failed\n", i,
                               is_end_point(i) ? "endpoint" : "root-complex");
index 71a8b69..f2231c2 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     board/amcc/katmai/init.o   (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 5ebe692..5cd822a 100644 (file)
@@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/errno.h>
 
 #if defined(CONFIG_PCI)
 #include <pci.h>
@@ -317,6 +318,8 @@ void pcie_setup_hoses(int busno)
                        ret = ppc4xx_init_pcie_endport(i);
                else
                        ret = ppc4xx_init_pcie_rootport(i);
+               if (ret == -ENODEV)
+                       continue;
                if (ret) {
                        printf("PCIE%d: initialization as %s failed\n", i,
                               is_end_point(i) ? "endpoint" : "root-complex");
index b769e94..738caa0 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x10000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index a44613d..bebb2b2 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 05362e0..569d78c 100644 (file)
@@ -8,8 +8,8 @@
 #define EPLD0_FLASH_SRAM_SEL_N 0x01    /* 0 SRAM at mem top, 1 small flash at mem top */
 
 #define EPLD1_CLK_CNTL0                0x80    /* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIX0_CNTL1      0x40    /* S*0 of 9531 */
-#define EPLD1_PCIX0_CNTL2      0x20    /* S*1 of 9531 */
+#define EPLD1_PCIL0_CNTL1      0x40    /* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2      0x20    /* S*1 of 9531 */
 #define EPLD1_CLK_CNTL3                0x10    /* FSEL-B1 of MPC9772 */
 #define EPLD1_CLK_CNTL4                0x08    /* FSEL-B0 of MPC9772 */
 #define EPLD1_MASTER_CLOCK6    0x04    /* clock source select 6 */
 #define EPLD3_STATUS_LED2      0x02    /* status LED 2 (1 = LED on) */
 #define EPLD3_STATUS_LED1      0x01    /* status LED 1 (1 = LED on) */
 
-#define EPLD4_PCIX0_VTH1       0x80    /* PCI-X 0 VTH1 status */
-#define EPLD4_PCIX0_VTH2       0x40    /* PCI-X 0 VTH2 status */
-#define EPLD4_PCIX0_VTH3       0x20    /* PCI-X 0 VTH3 status */
-#define EPLD4_PCIX0_VTH4       0x10    /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIL0_VTH1       0x80    /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2       0x40    /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3       0x20    /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4       0x10    /* PCI-X 0 VTH4 status */
 #define EPLD4_PCIX1_VTH1       0x08    /* PCI-X 1 VTH1 status */
 #define EPLD4_PCIX1_VTH2       0x04    /* PCI-X 1 VTH2 status */
 #define EPLD4_PCIX1_VTH3       0x02    /* PCI-X 1 VTH3 status */
 #define EPLD4_PCIX1_VTH4       0x01    /* PCI-X 1 VTH4 status */
 
-#define EPLD5_PCIX0_INT0       0x80    /* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIX0_INT1       0x40    /* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIX0_INT2       0x20    /* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIX0_INT3       0x10    /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIL0_INT0       0x80    /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1       0x40    /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2       0x20    /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3       0x10    /* PCIX0 INT3 status, write 0 to reset */
 #define EPLD5_PCIX1_INT0       0x08    /* PCIX1 INT0 status, write 0 to reset */
 #define EPLD5_PCIX1_INT1       0x04    /* PCIX1 INT1 status, write 0 to reset */
 #define EPLD5_PCIX1_INT2       0x02    /* PCIX1 INT2 status, write 0 to reset */
 #define EPLD5_PCIX1_INT3       0x01    /* PCIX1 INT3 status, write 0 to reset */
 
-#define EPLD6_PCIX0_RESET_CTL  0x80    /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIL0_RESET_CTL  0x80    /* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_PCIX1_RESET_CTL  0x40    /* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_ETH_INT_MODE     0x20    /* 0=IRQ5 recv's external eth int */
 #define EPLD6_PCIX2_RESET_CTL  0x10    /* 0=enable slot reset, 1=disable slot reset */
index 5f76672..a04f2af 100644 (file)
@@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 7c1bc82..12c5b60 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/luan/init.o     (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index fb0e7b7..d4277dd 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <fdt_support.h>
+#include <asm/errno.h>
 
 #if defined(CONFIG_PCI)
 #include <pci.h>
@@ -273,6 +274,8 @@ void pcie_setup_hoses(int busno)
                        ret = ppc4xx_init_pcie_endport(i);
                else
                        ret = ppc4xx_init_pcie_rootport(i);
+               if (ret == -ENODEV)
+                       continue;
                if (ret) {
                        printf("PCIE%d: initialization as %s failed\n", i,
                               is_end_point(i) ? "endpoint" : "root-complex");
index a44613d..bebb2b2 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index d776eda..0aa317e 100644 (file)
@@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 95cac85..b0b4c00 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/ocotea/init.o   (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 32eff52..7bda06e 100644 (file)
@@ -73,7 +73,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 17f831c..d42c802 100644 (file)
@@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index b580e0b..fb629e0 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x10000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 9393b65..e22dbec 100644 (file)
@@ -53,7 +53,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7798722..b9ec56b 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b7aa160..d37200d 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index e4e441b..a9a80e5 100644 (file)
@@ -39,13 +39,13 @@ void show_reset_reg(void)
        mfcpr(CPR0_PLLD,reg);
        printf("cpr_plld   = %#010lx\n",reg);
 
-       mfcpr(CPR0_PRIMAD,reg);
+       mfcpr(CPR0_PRIMAD0,reg);
        printf("cpr_primad = %#010lx\n",reg);
 
-       mfcpr(CPR0_PRIMBD,reg);
+       mfcpr(CPR0_PRIMBD0,reg);
        printf("cpr_primbd = %#010lx\n",reg);
 
-       mfcpr(CPR0_OPBD,reg);
+       mfcpr(CPR0_OPBD0,reg);
        printf("cpr_opbd   = %#010lx\n",reg);
 
        mfcpr(CPR0_PERD,reg);
@@ -106,59 +106,59 @@ void show_xbridge_info(void)
        printf("SDR0_XPLLD  = %#010lx\n", reg);
 
        printf("PCI-X Bridge Configure registers\n");
-       printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
-       printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
-       printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
-       printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
-       printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
-       printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
-       printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
-       printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
-       printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
-
-       printf("PCIX0_BAR0              = %#010lx\n", in32r(PCIX0_BAR0));
-       printf("PCIX0_BAR1              = %#010lx\n", in32r(PCIX0_BAR1));
-       printf("PCIX0_BAR2              = %#010lx\n", in32r(PCIX0_BAR2));
-       printf("PCIX0_BAR3              = %#010lx\n", in32r(PCIX0_BAR3));
-       printf("PCIX0_BAR4              = %#010lx\n", in32r(PCIX0_BAR4));
-       printf("PCIX0_BAR5              = %#010lx\n", in32r(PCIX0_BAR5));
-
-       printf("PCIX0_CISPTR            = %#010lx\n", in32r(PCIX0_CISPTR));
-       printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
-       printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
-       printf("PCIX0_EROMBA            = %#010lx\n", in32r(PCIX0_EROMBA));
-       printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
-       printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
-       printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
-       printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
-       printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
-
-       printf("PCIX0_BRDGOPT1          = %#010lx\n", in32r(PCIX0_BRDGOPT1));
-       printf("PCIX0_BRDGOPT2          = %#010lx\n", in32r(PCIX0_BRDGOPT2));
-
-       printf("PCIX0_POM0LAL           = %#010lx\n", in32r(PCIX0_POM0LAL));
-       printf("PCIX0_POM0LAH           = %#010lx\n", in32r(PCIX0_POM0LAH));
-       printf("PCIX0_POM0SA            = %#010lx\n", in32r(PCIX0_POM0SA));
-       printf("PCIX0_POM0PCILAL        = %#010lx\n", in32r(PCIX0_POM0PCIAL));
-       printf("PCIX0_POM0PCILAH        = %#010lx\n", in32r(PCIX0_POM0PCIAH));
-       printf("PCIX0_POM1LAL           = %#010lx\n", in32r(PCIX0_POM1LAL));
-       printf("PCIX0_POM1LAH           = %#010lx\n", in32r(PCIX0_POM1LAH));
-       printf("PCIX0_POM1SA            = %#010lx\n", in32r(PCIX0_POM1SA));
-       printf("PCIX0_POM1PCILAL        = %#010lx\n", in32r(PCIX0_POM1PCIAL));
-       printf("PCIX0_POM1PCILAH        = %#010lx\n", in32r(PCIX0_POM1PCIAH));
-       printf("PCIX0_POM2SA            = %#010lx\n", in32r(PCIX0_POM2SA));
-
-       printf("PCIX0_PIM0SA            = %#010lx\n", in32r(PCIX0_PIM0SA));
-       printf("PCIX0_PIM0LAL           = %#010lx\n", in32r(PCIX0_PIM0LAL));
-       printf("PCIX0_PIM0LAH           = %#010lx\n", in32r(PCIX0_PIM0LAH));
-       printf("PCIX0_PIM1SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-       printf("PCIX0_PIM1LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-       printf("PCIX0_PIM1LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-       printf("PCIX0_PIM2SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-       printf("PCIX0_PIM2LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-       printf("PCIX0_PIM2LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-
-       printf("PCIX0_XSTS              = %#010lx\n", in32r(PCIX0_STS));
+       printf("PCIL0_VENDID            = %#06x\n", in16r(PCIL0_VENDID));
+       printf("PCIL0_DEVID             = %#06x\n", in16r(PCIL0_DEVID));
+       printf("PCIL0_CMD               = %#06x\n", in16r(PCIL0_CMD));
+       printf("PCIL0_STATUS            = %#06x\n", in16r(PCIL0_STATUS));
+       printf("PCIL0_REVID             = %#04x\n", in8(PCIL0_REVID));
+       printf("PCIL0_CACHELS           = %#04x\n", in8(PCIL0_CACHELS));
+       printf("PCIL0_LATTIM            = %#04x\n", in8(PCIL0_LATTIM));
+       printf("PCIL0_HDTYPE            = %#04x\n", in8(PCIL0_HDTYPE));
+       printf("PCIL0_BIST              = %#04x\n", in8(PCIL0_BIST));
+
+       printf("PCIL0_BAR0              = %#010lx\n", in32r(PCIL0_BAR0));
+       printf("PCIL0_BAR1              = %#010lx\n", in32r(PCIL0_BAR1));
+       printf("PCIL0_BAR2              = %#010lx\n", in32r(PCIL0_BAR2));
+       printf("PCIL0_BAR3              = %#010lx\n", in32r(PCIL0_BAR3));
+       printf("PCIL0_BAR4              = %#010lx\n", in32r(PCIL0_BAR4));
+       printf("PCIL0_BAR5              = %#010lx\n", in32r(PCIL0_BAR5));
+
+       printf("PCIL0_CISPTR            = %#010lx\n", in32r(PCIL0_CISPTR));
+       printf("PCIL0_SBSSYSVID         = %#010x\n", in16r(PCIL0_SBSYSVID));
+       printf("PCIL0_SBSSYSID          = %#010x\n", in16r(PCIL0_SBSYSID));
+       printf("PCIL0_EROMBA            = %#010lx\n", in32r(PCIL0_EROMBA));
+       printf("PCIL0_CAP               = %#04x\n", in8(PCIL0_CAP));
+       printf("PCIL0_INTLN             = %#04x\n", in8(PCIL0_INTLN));
+       printf("PCIL0_INTPN             = %#04x\n", in8(PCIL0_INTPN));
+       printf("PCIL0_MINGNT            = %#04x\n", in8(PCIL0_MINGNT));
+       printf("PCIL0_MAXLTNCY          = %#04x\n", in8(PCIL0_MAXLTNCY));
+
+       printf("PCIL0_BRDGOPT1          = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+       printf("PCIL0_BRDGOPT2          = %#010lx\n", in32r(PCIL0_BRDGOPT2));
+
+       printf("PCIL0_POM0LAL           = %#010lx\n", in32r(PCIL0_POM0LAL));
+       printf("PCIL0_POM0LAH           = %#010lx\n", in32r(PCIL0_POM0LAH));
+       printf("PCIL0_POM0SA            = %#010lx\n", in32r(PCIL0_POM0SA));
+       printf("PCIL0_POM0PCILAL        = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+       printf("PCIL0_POM0PCILAH        = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+       printf("PCIL0_POM1LAL           = %#010lx\n", in32r(PCIL0_POM1LAL));
+       printf("PCIL0_POM1LAH           = %#010lx\n", in32r(PCIL0_POM1LAH));
+       printf("PCIL0_POM1SA            = %#010lx\n", in32r(PCIL0_POM1SA));
+       printf("PCIL0_POM1PCILAL        = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+       printf("PCIL0_POM1PCILAH        = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+       printf("PCIL0_POM2SA            = %#010lx\n", in32r(PCIL0_POM2SA));
+
+       printf("PCIL0_PIM0SA            = %#010lx\n", in32r(PCIL0_PIM0SA));
+       printf("PCIL0_PIM0LAL           = %#010lx\n", in32r(PCIL0_PIM0LAL));
+       printf("PCIL0_PIM0LAH           = %#010lx\n", in32r(PCIL0_PIM0LAH));
+       printf("PCIL0_PIM1SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+       printf("PCIL0_PIM1LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+       printf("PCIL0_PIM1LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+       printf("PCIL0_PIM2SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+       printf("PCIL0_PIM2LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+       printf("PCIL0_PIM2LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+
+       printf("PCIL0_XSTS              = %#010lx\n", in32r(PCIL0_STS));
 }
 
 int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
index 4a0573e..0c20faf 100644 (file)
@@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 75b7fc9..c043f69 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/taishan/init.o  (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index f6cbe13..d7a7857 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index e31f071..b8646d5 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/yosemite/init.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 1ec13eb..7ceccfa 100644 (file)
@@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index 60135b9..2d44c64 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/amcc/yucca/init.o    (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 033bdd2..d8f4bcb 100644 (file)
@@ -32,6 +32,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/4xx_pcie.h>
+#include <asm/errno.h>
 
 #include "yucca.h"
 
@@ -632,27 +633,27 @@ void pci_target_init(struct pci_controller * hose )
        /*-------------------------------------------------------------------+
         * Disable everything
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*-------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*-------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -830,6 +831,8 @@ void pcie_setup_hoses(int busno)
                        yucca_setup_pcie_fpga_rootpoint(i);
                        ret = ppc4xx_init_pcie_rootport(i);
                }
+               if (ret == -ENODEV)
+                       continue;
                if (ret) {
                        printf("PCIE%d: initialization as %s failed\n", i,
                               is_end_point(i) ? "endpoint" : "root-complex");
index a4c48d6..707203d 100644 (file)
@@ -72,7 +72,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index a46deea..518944e 100644 (file)
@@ -34,9 +34,7 @@
  */
 
 #include <common.h>
-#ifdef CONFIG_PCI
 #include <netdev.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -127,9 +125,16 @@ extern void dram_query(void);
        return 0;
 }
 
-#ifdef CONFIG_PCI
+#ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
 {
-       return pci_eth_init(bis);
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_PCI
+       rc += pci_eth_init(bis);
+#endif
+       return rc;
 }
 #endif
index 197bc89..6e836dd 100644 (file)
@@ -34,6 +34,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -89,3 +90,14 @@ int dram_init (void)
 {
        return 0;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index d5f0b7c..8727dee 100644 (file)
@@ -26,6 +26,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include "psd4256.h"
 #include "flash-defines.h"
 
@@ -57,3 +58,10 @@ int misc_init_r(void)
 
        return 0;
 }
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index 7108dda..a226910 100644 (file)
@@ -26,6 +26,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include "bf533-stamp.h"
 
@@ -283,3 +284,10 @@ void __led_toggle(led_id_t mask)
 }
 
 #endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index bbee989..15916fa 100644 (file)
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <config.h>
 #include <asm/blackfin.h>
 
@@ -25,3 +26,10 @@ phys_size_t initdram(int board_type)
        gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
        return gd->bd->bi_memsize;
 }
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index 5aede17..e5d7eb3 100644 (file)
@@ -26,6 +26,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -43,3 +44,10 @@ phys_size_t initdram(int board_type)
        gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
        return gd->bd->bi_memsize;
 }
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index b671899..f55ab97 100644 (file)
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -44,3 +45,10 @@ void swap_to(int device_id)
        SSYNC();
 }
 #endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index 61650a8..2d0efb3 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index dbec986..ad36953 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 307894f..59346bc 100644 (file)
@@ -26,6 +26,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -71,3 +72,14 @@ int dram_init (void)
 
        return 0;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index 7eb761d..ab0bf3b 100644 (file)
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -23,3 +24,10 @@ phys_size_t initdram(int board_type)
        gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
        return gd->bd->bi_memsize;
 }
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index 5bce9eb..f21a015 100644 (file)
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -23,3 +24,10 @@ phys_size_t initdram(int board_type)
        gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
        return gd->bd->bi_memsize;
 }
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+       return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
index 3a72bd3..5887f77 100644 (file)
@@ -52,7 +52,6 @@ SECTIONS
   {
     cpu/mpc5xxx/start.o        (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
     . = ALIGN(16);
     *(.eh_frame)
index 3ea6f1c..2fecb0f 100644 (file)
@@ -54,7 +54,6 @@ SECTIONS
   {
     *(.text)
     common/env_embedded.o(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ea85389..a2d940f 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 6d8d555..21eb655 100644 (file)
@@ -27,6 +27,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -223,3 +224,14 @@ dram_init (void)
                PHYS_SDRAM_3_SIZE +
                PHYS_SDRAM_4_SIZE );
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index 86c8ecb..bd80df6 100644 (file)
@@ -78,7 +78,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 338392a..970628d 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0aa6f8f..b58ccc5 100644 (file)
@@ -79,7 +79,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 565e021..ba37c1b 100644 (file)
@@ -79,7 +79,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b36827d..ee7f59e 100644 (file)
@@ -73,7 +73,6 @@ SECTIONS
     lib_generic/zlib.o         (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0a44748..87f284c 100644 (file)
@@ -92,8 +92,8 @@ int board_eth_init(bd_t *bis)
 static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
 {
        struct nand_chip        *this = mtd->priv;
-       u32                     wbase = (u32) this->IO_ADDR_W;
-       u32                     rbase = (u32) this->IO_ADDR_R;
+       unsigned long           wbase = (unsigned long) this->IO_ADDR_W;
+       unsigned long           rbase = (unsigned long) this->IO_ADDR_R;
 
        if (chip == 1) {
                __set_bit(14, &wbase);
diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile
new file mode 100644 (file)
index 0000000..26b0705
--- /dev/null
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := $(BOARD).o
+SOBJS  :=
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk
new file mode 100644 (file)
index 0000000..d67df02
--- /dev/null
@@ -0,0 +1,6 @@
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c
new file mode 100644 (file)
index 0000000..e89786e
--- /dev/null
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_defs.h>
+#include <asm/arch/nand_defs.h>
+#include "../common/misc.h"
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       struct davinci_gpio *gpio01_base =
+                       (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
+       struct davinci_gpio *gpio23_base =
+                       (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
+       struct davinci_gpio *gpio67_base =
+                       (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+       gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       /* GIO 9 & 10 are used for IO */
+       writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
+
+       /* Interrupt set GIO 9 */
+       writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
+
+       /* set GIO 9 input */
+       writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
+
+       /* Both edge trigger GIO 9 */
+       writel((readl(&gpio01_base->set_rising) | (1 << 9)),
+                                               &gpio01_base->set_rising);
+       writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
+
+       /* output low */
+       writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
+                                               &gpio01_base->set_data);
+
+       /* set GIO 10 output */
+       writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
+
+       /* output high */
+       writel((readl(&gpio01_base->set_data) | (1 << 10)),
+                                               &gpio01_base->set_data);
+
+       /* set GIO 32 output */
+       writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
+
+       /* output High */
+       writel((readl(&gpio23_base->set_data) | (1 << 0)),
+                                               &gpio23_base->set_data);
+
+       /* Enable UART1 MUX Lines */
+       writel((readl(PINMUX0) & ~3), PINMUX0);
+       writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
+       writel((readl(&gpio67_base->set_data) | (1 << 6)),
+                                               &gpio67_base->set_data);
+
+       return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+       return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+       davinci_nand_init(nand);
+
+       return 0;
+}
+#endif
index 5b97060..290eb99 100644 (file)
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2009 Texas Instruments Incorporated
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -79,8 +80,8 @@ int board_eth_init(bd_t *bis)
 static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
 {
        struct nand_chip        *this = mtd->priv;
-       u32                     wbase = (u32) this->IO_ADDR_W;
-       u32                     rbase = (u32) this->IO_ADDR_R;
+       unsigned long           wbase = (unsigned long) this->IO_ADDR_W;
+       unsigned long           rbase = (unsigned long) this->IO_ADDR_R;
 
        if (chip == 1) {
                __set_bit(14, &wbase);
diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile
new file mode 100644 (file)
index 0000000..26b0705
--- /dev/null
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := $(BOARD).o
+SOBJS  :=
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk
new file mode 100644 (file)
index 0000000..ca801c2
--- /dev/null
@@ -0,0 +1,2 @@
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
new file mode 100644 (file)
index 0000000..9605818
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       return 0;
+}
+
index 84ff47e..a294213 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <i2c.h>
 #include <da9030.h>
 #include <malloc.h>
@@ -363,3 +364,14 @@ void hw_watchdog_reset(void)
        i2c_reg_write(addr, SYS_CONTROL_A, val);
 }
 #endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index aa39611..ecea5b3 100644 (file)
@@ -320,36 +320,6 @@ static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                        ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
 }
 
-/* Relocate the command table function pointers when running in RAM */
-int mtc_cmd_init_r(void)
-{
-       cmd_tbl_t *cmdtp;
-
-       for (cmdtp = &cmd_mtc_sub[0]; cmdtp !=
-            &cmd_mtc_sub[ARRAY_SIZE(cmd_mtc_sub)]; cmdtp++) {
-               ulong addr;
-
-               addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
-               cmdtp->cmd =
-                   (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
-
-               addr = (ulong)(cmdtp->name) + gd->reloc_off;
-               cmdtp->name = (char *)addr;
-
-               if (cmdtp->usage) {
-                       addr = (ulong)(cmdtp->usage) + gd->reloc_off;
-                       cmdtp->usage = (char *)addr;
-               }
-#ifdef CONFIG_SYS_LONGHELP
-               if (cmdtp->help) {
-                       addr = (ulong)(cmdtp->help) + gd->reloc_off;
-                       cmdtp->help = (char *)addr;
-               }
-#endif
-       }
-       return 0;
-}
-
 int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
        cmd_tbl_t *c;
index 9d77e54..cc6087b 100644 (file)
@@ -240,7 +240,6 @@ void board_get_enetaddr (uchar * enet)
 
 int misc_init_r(void)
 {
-       extern int mtc_cmd_init_r (void);
        uchar enetaddr[6];
 
        if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
@@ -248,7 +247,6 @@ int misc_init_r(void)
                eth_setenv_enetaddr("ethaddr", enetaddr);
        }
 
-       mtc_cmd_init_r();
        return 0;
 }
 
index ab8e7be..c215f5f 100644 (file)
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <SA-1100.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -53,3 +54,14 @@ int dram_init (void)
 
        return (0);
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ee74eb9..5c847fb 100644 (file)
@@ -56,7 +56,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index dbec986..ad36953 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b4e093c..46dca96 100644 (file)
@@ -55,7 +55,6 @@ SECTIONS
     cpu/mpc8xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 82e8dce..bfe8513 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b3849de..70b84e4 100644 (file)
@@ -54,7 +54,6 @@ SECTIONS
   {
     cpu/mpc8xx/start.o (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
     . = ALIGN(16);
     *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
index e62896f..261ccfb 100644 (file)
@@ -78,7 +78,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 2645e84..9207fe0 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0221e30..2247109 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o         (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 005957e..285c901 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0221e30..2247109 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o         (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 47e946f..eecae0a 100644 (file)
@@ -48,7 +48,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        u32 la, ptm1la;
 
 #if defined(CONFIG_440)
-       ptm1la = in32r(PCIX0_PTM1LA);
+       ptm1la = in32r(PCIL0_PTM1LA);
 #else
        ptm1la = in32r(PTM1LA);
 #endif
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 77674b5..b044649 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 166d0d1..65ad2f2 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 056f455..d0e52cb 100644 (file)
@@ -435,26 +435,26 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index 7360349..3b6c096 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 005957e..285c901 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 1b50b6d..34884b6 100644 (file)
@@ -75,7 +75,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 005957e..285c901 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 74f1d87..178a755 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 1af431b..476e940 100644 (file)
@@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                /* map PCI address at 0xc0000000 in PLB space */
 
                /* PMM1 Mask/Attribute - disabled b4 setting */
-               out32r(PCIX0_PMM1MA, 0x00000000);
+               out32r(PCIL0_PMM1MA, 0x00000000);
                /* PMM1 Local Address */
-               out32r(PCIX0_PMM1LA, 0xc0000000);
+               out32r(PCIL0_PMM1LA, 0xc0000000);
                /* PMM1 PCI Low Address */
-               out32r(PCIX0_PMM1PCILA, pciaddr);
+               out32r(PCIL0_PMM1PCILA, pciaddr);
                /* PMM1 PCI High Address */
-               out32r(PCIX0_PMM1PCIHA, 0x00000000);
+               out32r(PCIL0_PMM1PCIHA, 0x00000000);
                /* 256MB + No prefetching, and enable region */
-               out32r(PCIX0_PMM1MA, 0xf0000001);
+               out32r(PCIL0_PMM1MA, 0xf0000001);
        } else {
                printf("Usage:\npmm %s\n", cmdtp->help);
        }
index a2eda32..f92bbff 100644 (file)
@@ -442,9 +442,9 @@ int pmc440_init_fpga(void)
 {
        char *s;
 
-       debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
-             __FUNCTION__, __LINE__, gd->reloc_off);
-       fpga_init(gd->reloc_off);
+       debug("%s:%d: Initialize FPGA interface\n",
+             __FUNCTION__, __LINE__);
+       fpga_init();
 
        fpga_serialslave_init ();
        debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
index 26a8282..6585fed 100644 (file)
@@ -23,7 +23,7 @@
 #include <asm-ppc/mmu.h>
 #include <config.h>
 
-/**************************************************************************
+/*
  * TLB TABLE
  *
  * This table is used by the cpu boot code to setup the initial tlb
@@ -32,7 +32,7 @@
  *
  *  Pointer to the table is returned in r1
  *
- *************************************************************************/
+ */
     .section .bootpg,"ax"
     .globl tlbtab
 
@@ -49,12 +49,7 @@ tlbtab:
        tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
 #endif
 
-       /* TLB-entry for DDR SDRAM (Up to 2GB) */
-#ifdef CONFIG_4xx_DCACHE
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
-#else
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-#endif
+       /* TLB entries for DDR2 SDRAM are generated dynamically */
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
index f0f9bff..ec92552 100644 (file)
@@ -208,7 +208,7 @@ int misc_init_f(void)
 
        if (getenv("pciearly") && (!is_monarch())) {
                printf("PCI:   early target init\n");
-               pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+               pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
                pci_target_init(&hose);
        }
        return 0;
@@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
                                                /* and enable region */
 
        if (!is_monarch()) {
                ptmla_str = getenv("ptm1la");
                ptmms_str = getenv("ptm1ms");
                if(NULL != ptmla_str && NULL != ptmms_str ) {
-                       out32r(PCIX0_PTM1MS,
+                       out32r(PCIL0_PTM1MS,
                               simple_strtoul(ptmms_str, NULL, 16));
-                       out32r(PCIX0_PTM1LA,
+                       out32r(PCIL0_PTM1LA,
                               simple_strtoul(ptmla_str, NULL, 16));
                } else {
                        /* BAR1: default top 64MB of RAM */
-                       out32r(PCIX0_PTM1MS, 0xfc000001);
-                       out32r(PCIX0_PTM1LA, 0x0c000000);
+                       out32r(PCIL0_PTM1MS, 0xfc000001);
+                       out32r(PCIL0_PTM1LA, 0x0c000000);
                }
        } else {
                /* BAR1: default: complete 256MB RAM */
-               out32r(PCIX0_PTM1MS, 0xf0000001);
-               out32r(PCIX0_PTM1LA, 0x00000000);
+               out32r(PCIL0_PTM1MS, 0xf0000001);
+               out32r(PCIL0_PTM1LA, 0x00000000);
        }
 
        ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
        ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
        if(NULL != ptmla_str && NULL != ptmms_str ) {
-               out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
-               out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+               out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+               out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
        } else {
                /* BAR2: default: 4MB FPGA */
-               out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
-               out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+               out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+               out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
        }
 
        if (is_monarch()) {
index bb46ecc..c3528bc 100644 (file)
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
+ *
  * (C) Copyright 2006
  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include <ppc440.h>
 
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
+struct sdram_conf_s {
+       ulong size;
+       int rows;
+       int banks;
+};
 
-#if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val)      133000000
-#endif
+struct sdram_conf_s sdram_conf[] = {
+       {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
+       {(512 << 20),  13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
+       {(256 << 20),  13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
+};
 
-/*************************************************************************
- *
+/*
  * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
+ */
+int initdram_by_rb(int rows, int banks)
 {
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#if !defined(CONFIG_NAND_SPL)
        ulong speed = get_bus_freq(0);
-#else
-       ulong speed = 133333333;        /* 133MHz is on the safe side   */
-#endif
 
        mtsdram(DDR0_02, 0x00000000);
 
@@ -89,21 +89,25 @@ phys_size_t initdram (int board_type)
        mtsdram(DDR0_27, 0x0000682B);
        mtsdram(DDR0_28, 0x00000000);
        mtsdram(DDR0_31, 0x00000000);
-       mtsdram(DDR0_42, 0x01000006);
-       mtsdram(DDR0_43, 0x030A0200);
+
+       mtsdram(DDR0_42,
+               DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+               0x00000006);
+       mtsdram(DDR0_43,
+               DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
+               0x030A0200);
+
        mtsdram(DDR0_44, 0x00000003);
        mtsdram(DDR0_02, 0x00000001);
 
        denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
 
 #ifdef CONFIG_DDR_DATA_EYE
-       /* -----------------------------------------------------------+
+       /*
         * Perform data eye search if requested.
-        * ----------------------------------------------------------*/
+        */
        denali_core_search_data_eye();
 #endif
-
        /*
         * Clear possible errors resulting from data-eye-search.
         * If not done, then we could get an interrupt later on when
@@ -111,5 +115,35 @@ phys_size_t initdram (int board_type)
         */
        set_mcsr(get_mcsr());
 
-       return (CONFIG_SYS_MBYTES_SDRAM << 20);
+       return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t size;
+       int n;
+
+       /* go through supported memory configurations */
+       for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
+               size = sdram_conf[n].size;
+
+               /* program TLB entries */
+               program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
+                           TLB_WORD2_I_ENABLE);
+
+               /*
+                * setup denali core
+                */
+               initdram_by_rb(sdram_conf[n].rows,
+                              sdram_conf[n].banks);
+
+               /* check for suitable configuration */
+               if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
+                       return size;
+
+               /* delete TLB entries */
+               remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
+       }
+
+       return 0;
 }
index b580e0b..fb629e0 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     . = ALIGN(0x10000);
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7360349..3b6c096 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 005957e..285c901 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 57aabed..3e4490e 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index eb3d487..1d34e68 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
     . = env_offset;
     common/env_embedded.o(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 28f8804..1af61fb 100644 (file)
@@ -71,7 +71,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0b4f0d4..af8a4a2 100644 (file)
@@ -165,7 +165,7 @@ int board_init(void)
 
        /* arch number of the board */
 #if defined(CONFIG_CPU9G20)
-       gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
+       gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
 #elif defined(CONFIG_CPU9260)
        gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
 #endif
index 632921a..d021331 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7a9726f..721aaac 100644 (file)
@@ -52,7 +52,7 @@
 #define    IIC_EXTSTS  (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
 #define    IIC_LSADR   (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
 #define    IIC_HSADR   (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV  (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_CLKDIV  (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
 #define    IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
 #define    IIC_XFRCNT  (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
 #define    IIC_XTCNTLSS        (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
@@ -537,7 +537,7 @@ read_spd:
        WRITE_I2C(IICHSADR, 0x00)       /* clear hi slave address */
        WRITE_I2C(IICSTS, 0x08)         /* update status register */
        WRITE_I2C(IICEXTSTS, 0x8f)
-       WRITE_I2C(IICCLKDIV, 0x05)
+       WRITE_I2C(IIC0_CLKDIV, 0x05)
        WRITE_I2C(IICINTRMSK, 0x00)     /* no interrupts */
        WRITE_I2C(IICXFRCNT, 0x00)      /* clear transfer count */
        WRITE_I2C(IICXTCNTLSS, 0xf0)    /* clear extended control & stat */
index 2798dc8..d2b28e1 100644 (file)
@@ -77,7 +77,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b39ef14..ce3e32e 100644 (file)
@@ -56,7 +56,6 @@ SECTIONS
     common/env_embedded.o      (.ppcenv)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 67d37ae..0a3b958 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 1c8180a..877e82c 100644 (file)
@@ -55,7 +55,6 @@ SECTIONS
     cpu/mpc8xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index dbec986..ad36953 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 13bd73c..2fa3650 100644 (file)
@@ -169,11 +169,11 @@ phys_size_t initdram(int board_type)
         * Elpida MDDRC and initialization settings are an alternative
         * to the Default Micron ones for all but the earliest Rev 4 boards
         */
-       u32 elpida_mddrc_config[4] = {
-               CONFIG_SYS_MDDRC_TIME_CFG0,
-               CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
-               CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
-               CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+       ddr512x_config_t elpida_mddrc_config = {
+               .ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+               .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+               .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+               .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
        };
 
        u32 elpida_init_sequence[] = {
@@ -229,7 +229,7 @@ phys_size_t initdram(int board_type)
        if (is_micron()) {
                msize = fixed_sdram(NULL, NULL, 0);
        } else {
-               msize = fixed_sdram(elpida_mddrc_config,
+               msize = fixed_sdram(&elpida_mddrc_config,
                                elpida_init_sequence,
                                sizeof(elpida_init_sequence)/sizeof(u32));
        }
index cd11f39..247779f 100644 (file)
@@ -63,7 +63,6 @@ SECTIONS
 /*    common/env_embedded.o(.text) */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 80de6f8..73e7c21 100644 (file)
@@ -276,7 +276,6 @@ pci_init_board(void)
 {
        volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
        struct pci_controller *hose = &pci1_hose;
-       struct pci_config_table *table;
        struct pci_region *r = hose->regions;
 
        uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;      /* PORDEVSR[15] */
@@ -312,12 +311,6 @@ pci_init_board(void)
                               PCI_REGION_IO);
                hose->region_count = r - hose->regions;
 
-               /* relocate config table pointers */
-               hose->config_table = \
-                       (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
-               for (table = hose->config_table; table && table->vendor; table++)
-                       table->config_device += gd->reloc_off;
-
                hose->first_busno=first_free_busno;
 
                fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
index 5cc88ae..b573807 100644 (file)
@@ -61,7 +61,6 @@ SECTIONS
     lib_ppc/extable.o (.text)
     lib_generic/zlib.o (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
    }
     _etext = .;
index e188722..2b98b5a 100644 (file)
@@ -62,7 +62,6 @@ SECTIONS
     lib_generic/zlib.o (.text)
     drivers/bios_emulator/atibios.o (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
    }
     _etext = .;
index 8c01016..0799275 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 105a747..7fe85b8 100644 (file)
@@ -19,6 +19,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <config.h>
 #include <asm/leon.h>
 
@@ -37,3 +38,14 @@ int misc_init_r(void)
 {
        return 0;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index 2904d32..7241c6d 100644 (file)
@@ -19,6 +19,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <config.h>
 #include <asm/leon.h>
 
@@ -37,3 +38,14 @@ int misc_init_r(void)
 {
        return 0;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index d803625..689c808 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7cc1bf2..90dbe52 100644 (file)
@@ -239,22 +239,22 @@ void pci_target_init(struct pci_controller *hose)
         *   Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);
-       out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);
-       out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);
-       out32r(PCIX0_PTM1LA, 0);
-       out32r(PCIX0_PTM2MS, 0);
-       out32r(PCIX0_PTM2LA, 0);
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);
+       out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);
+       out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);
+       out32r(PCIL0_PTM1LA, 0);
+       out32r(PCIL0_PTM2MS, 0);
+       out32r(PCIL0_PTM2LA, 0);
 
        /*
         * Set up Configuration registers
index 77f0aae..6ab36ee 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/gdsys/gdppc440etx/init.o     (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 2cd2e6d..b42e908 100644 (file)
@@ -154,27 +154,27 @@ void pci_target_init(struct pci_controller *hose)
        /*
         * Disable everything
         */
-       out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
        /*
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         */
-       out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIX0_PIM0LAH, 0);
-       out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIX0_BAR0, 0);
+       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out_le32((void *)PCIL0_PIM0LAH, 0);
+       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out_le32((void *)PCIL0_BAR0, 0);
 
        /*
         * Program the board's subsystem id/vendor id
         */
-       out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index c1cbd1c..624c4c1 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     board/gdsys/intip/init.o   (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b95eb5c..75202ca 100644 (file)
@@ -60,7 +60,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 29cad2e..d42c500 100644 (file)
@@ -193,8 +193,9 @@ int gen860t_init_fpga (void)
 {
        int i;
 
-       PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
-       fpga_init (gd->reloc_off);
+       PRINTF ("%s:%d: Initialize FPGA interface\n",
+               __FUNCTION__, __LINE__);
+       fpga_init ();
        fpga_selectmap_init ();
 
        for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
index 9785639..7b83b25 100644 (file)
@@ -57,7 +57,6 @@ SECTIONS
   {
     cpu/mpc8xx/start.o (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index fbe3c70..8f40b30 100644 (file)
@@ -56,7 +56,6 @@ SECTIONS
   {
     cpu/mpc8xx/start.o         (.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ee0b719..716efcd 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     . = env_offset;
     common/env_embedded.o(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 61fdfe5..3568e6d 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     . = env_offset;
     common/env_embedded.o(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 8826550..f6175d9 100644 (file)
@@ -55,7 +55,6 @@ SECTIONS
     cpu/mpc8xx/start.o(.text)
     *(.text)
     common/env_embedded.o(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 02216fb..7b74cb7 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 78456e6..3801206 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 03fefec..52d66a2 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ea85389..a2d940f 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 9a28cfd..b43be81 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
 */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index dbd1f9d..653e0be 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index c645b05..27b79ec 100644 (file)
@@ -177,16 +177,6 @@ void flash_preinit(void)
        clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
 }
 
-int misc_init_r (void) {
-       extern int inkadiag_init_r (void);
-
-       /*
-        * The command table used for the subcommands of inkadiag
-        * needs to be relocated manually.
-        */
-       return inkadiag_init_r();
-}
-
 int misc_init_f (void)
 {
        volatile struct mpc5xxx_gpio    *gpio    =
index 3761ef6..0a75abd 100644 (file)
@@ -484,31 +484,3 @@ U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
           "[inkadiag what ...]\n"
           "    - perform a diagnosis on inka hardware\n"
           "'inkadiag' performs hardware tests.");
-
-/* Relocate the command table function pointers when running in RAM */
-int inkadiag_init_r (void) {
-       cmd_tbl_t *cmdtp;
-
-       for (cmdtp = &cmd_inkadiag_sub[0]; cmdtp !=
-                    &cmd_inkadiag_sub[ARRAY_SIZE(cmd_inkadiag_sub)]; cmdtp++) {
-               ulong addr;
-
-               addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
-               cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
-
-               addr = (ulong)(cmdtp->name) + gd->reloc_off;
-               cmdtp->name = (char *)addr;
-
-               if (cmdtp->usage) {
-                       addr = (ulong)(cmdtp->usage) + gd->reloc_off;
-                       cmdtp->usage = (char *)addr;
-               }
-#ifdef CONFIG_SYS_LONGHELP
-               if (cmdtp->help) {
-                       addr = (ulong)(cmdtp->help) + gd->reloc_off;
-                       cmdtp->help = (char *)addr;
-               }
-#endif
-       }
-       return 0;
-}
index c2b88ae..3412f10 100644 (file)
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/mach-types.h>
 
@@ -182,3 +183,14 @@ void show_boot_progress (int status)
 
        return;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
+}
+#endif
index b47ae8e..a786bf2 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     common/env_embedded.o(.text)
 **/
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index e8a47f7..dc2f6e1 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 **/
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index ab51bd8..8d7ff70 100644 (file)
@@ -55,7 +55,6 @@ SECTIONS
     cpu/mpc8xx/start.o (.text)
     common/env_embedded.o(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 4d49f1b..b5206c5 100644 (file)
@@ -65,7 +65,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 12d3938..6d0a21c 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
 /*    common/env_embedded.o(.text)*/
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 5af36c9..a8057f2 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
     common/env_embedded.o      (.ppcenv)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 40a097c..8c674a2 100644 (file)
@@ -679,29 +679,29 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA,
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA,
               CONFIG_SYS_PCI_MEMBASE);         /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA,
+       out32r(PCIL0_PMM1LA,
               CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA,
+       out32r(PCIL0_PMM1PCILA,
               CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index c175f91..cbad866 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 7798722..b9ec56b 100644 (file)
@@ -68,7 +68,6 @@ SECTIONS
     cpu/ppc4xx/start.o (.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index f2b6650..79b886a 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
 */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0f6ae69..83fdc15 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index f2b6650..79b886a 100644 (file)
@@ -69,7 +69,6 @@ SECTIONS
 */
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index 0f6ae69..83fdc15 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index b9fa2d6..854ed68 100644 (file)
@@ -66,7 +66,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index d5e2c1d..3b4799e 100644 (file)
@@ -64,7 +64,6 @@ SECTIONS
     common/env_embedded.o(.text)
 
     *(.text)
-    *(.fixup)
     *(.got1)
   }
   _etext = .;
index d9e2ae5..dadbeb6 100644 (file)
@@ -50,9 +50,6 @@
  * The details of the setting of the serial gpmc setup are not available.
  * The values were provided by another party.
  */
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-                       u32 size);
-
 static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
        0x00011000,
        0x001F1F01,
@@ -129,7 +126,7 @@ int board_init (void)
 
        /* Configure console support on zoom2 */
        gpmc_config = gpmc_serial_TL16CP754C;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4],
+       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
                        SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
 
        /* board id for Linux */