Merge branch 'master' of git://git.denx.de/u-boot-imx
authorTom Rini <trini@ti.com>
Mon, 27 Oct 2014 13:08:42 +0000 (09:08 -0400)
committerTom Rini <trini@ti.com>
Mon, 27 Oct 2014 13:08:42 +0000 (09:08 -0400)
561 files changed:
Makefile
README
arch/Kconfig
arch/arm/Kconfig
arch/arm/cpu/arm926ejs/at91/led.c
arch/arm/cpu/arm926ejs/kirkwood/Makefile
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
arch/arm/cpu/arm926ejs/kirkwood/mpp.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/armada-xp/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/armada-xp/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/keystone/Kconfig
arch/arm/cpu/armv7/keystone/Makefile
arch/arm/cpu/armv7/keystone/clock-k2l.c [new file with mode: 0644]
arch/arm/cpu/armv7/keystone/clock.c
arch/arm/cpu/armv7/keystone/cmd_clock.c
arch/arm/cpu/armv7/keystone/cmd_ddr3.c [new file with mode: 0644]
arch/arm/cpu/armv7/keystone/ddr3.c
arch/arm/cpu/armv7/keystone/init.c
arch/arm/cpu/armv7/keystone/msmc.c
arch/arm/cpu/armv7/keystone/spl.c [deleted file]
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap3/Kconfig
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/emif4.c
arch/arm/cpu/armv7/omap3/sys_info.c
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
arch/arm/cpu/armv7/sunxi/Makefile
arch/arm/cpu/armv7/sunxi/board.c
arch/arm/cpu/armv7/sunxi/clock_sun4i.c
arch/arm/cpu/armv7/sunxi/clock_sun6i.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/cpu_info.c
arch/arm/cpu/armv7/sunxi/dram.c
arch/arm/cpu/armv7/sunxi/prcm.c [new file with mode: 0644]
arch/arm/cpu/armv7/tegra-common/Kconfig
arch/arm/cpu/armv7/tegra20/display.c
arch/arm/cpu/armv7/tegra30/Kconfig
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c [new file with mode: 0644]
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c [new file with mode: 0644]
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c [new file with mode: 0644]
arch/arm/cpu/tegra-common/board.c
arch/arm/cpu/tegra-common/sys_info.c
arch/arm/dts/Makefile
arch/arm/dts/am335x-bone-common.dtsi
arch/arm/dts/dt-bindings/gpio/gpio.h [deleted file]
arch/arm/dts/exynos4.dtsi
arch/arm/dts/exynos4210-origen.dts
arch/arm/dts/exynos4210-pinctrl-uboot.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4210-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4210-smdkv310.dts
arch/arm/dts/exynos4210-trats.dts
arch/arm/dts/exynos4210-universal_c210.dts
arch/arm/dts/exynos4210.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4412-odroid.dts
arch/arm/dts/exynos4412-trats2.dts
arch/arm/dts/exynos4412.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4x12-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/exynos4x12.dtsi [new file with mode: 0644]
arch/arm/dts/exynos5.dtsi
arch/arm/dts/exynos5250-pinctrl-uboot.dtsi [new file with mode: 0644]
arch/arm/dts/exynos5250-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/exynos5250-smdk5250.dts
arch/arm/dts/exynos5250-snow.dts
arch/arm/dts/exynos5250.dtsi
arch/arm/dts/exynos5420-peach-pit.dts
arch/arm/dts/exynos5420-smdk5420.dts
arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi [new file with mode: 0644]
arch/arm/dts/exynos54xx-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/exynos54xx.dtsi
arch/arm/dts/s5pc100-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/s5pc110-pinctrl.dtsi [new file with mode: 0644]
arch/arm/dts/s5pc1xx-goni.dts
arch/arm/dts/s5pc1xx-smdkc100.dts
arch/arm/dts/tegra20-trimslice.dts
arch/arm/dts/tegra30-apalis.dts [new file with mode: 0644]
arch/arm/dts/tegra30-beaver.dts
arch/arm/dts/tegra30-cardhu.dts
arch/arm/dts/tegra30-colibri.dts
arch/arm/imx-common/cpu.c
arch/arm/imx-common/i2c-mxv7.c
arch/arm/imx-common/misc.c
arch/arm/include/asm/arch-am33xx/mux.h
arch/arm/include/asm/arch-armada-xp/config.h [new file with mode: 0644]
arch/arm/include/asm/arch-armada-xp/cpu.h [new file with mode: 0644]
arch/arm/include/asm/arch-armada-xp/soc.h [new file with mode: 0644]
arch/arm/include/asm/arch-bcm2835/gpio.h
arch/arm/include/asm/arch-bcm2835/mbox.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-keystone/clock-k2e.h
arch/arm/include/asm/arch-keystone/clock-k2hk.h
arch/arm/include/asm/arch-keystone/clock-k2l.h [new file with mode: 0644]
arch/arm/include/asm/arch-keystone/clock.h
arch/arm/include/asm/arch-keystone/ddr3.h
arch/arm/include/asm/arch-keystone/emac_defs.h [deleted file]
arch/arm/include/asm/arch-keystone/hardware-k2e.h
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
arch/arm/include/asm/arch-keystone/hardware-k2l.h [new file with mode: 0644]
arch/arm/include/asm/arch-keystone/hardware.h
arch/arm/include/asm/arch-keystone/msmc.h
arch/arm/include/asm/arch-keystone/spl.h [deleted file]
arch/arm/include/asm/arch-keystone/xhci-keystone.h [new file with mode: 0644]
arch/arm/include/asm/arch-kirkwood/config.h
arch/arm/include/asm/arch-kirkwood/cpu.h
arch/arm/include/asm/arch-kirkwood/gpio.h
arch/arm/include/asm/arch-kirkwood/soc.h [moved from arch/arm/include/asm/arch-kirkwood/kirkwood.h with 90% similarity]
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-mvebu/spi.h [moved from arch/arm/include/asm/arch-kirkwood/spi.h with 100% similarity]
arch/arm/include/asm/arch-mxs/sys_proto.h
arch/arm/include/asm/arch-omap3/mux.h
arch/arm/include/asm/arch-omap3/sys_proto.h
arch/arm/include/asm/arch-s5pc1xx/gpio.h
arch/arm/include/asm/arch-socfpga/spl.h [deleted file]
arch/arm/include/asm/arch-sunxi/clock.h
arch/arm/include/asm/arch-sunxi/clock_sun4i.h
arch/arm/include/asm/arch-sunxi/clock_sun6i.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/cpu.h
arch/arm/include/asm/arch-sunxi/gpio.h
arch/arm/include/asm/arch-sunxi/mmc.h
arch/arm/include/asm/arch-sunxi/prcm.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/timer.h
arch/arm/include/asm/arch-sunxi/watchdog.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/board.h
arch/arm/include/asm/arch-tegra114/mc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/tegra.h
arch/arm/include/asm/arch-tegra114/tegra114_spi.h [deleted file]
arch/arm/include/asm/arch-tegra20/mc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/tegra.h
arch/arm/include/asm/arch-tegra20/tegra20_sflash.h [deleted file]
arch/arm/include/asm/arch-tegra20/tegra20_slink.h [deleted file]
arch/arm/include/asm/arch-tegra30/mc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra30/tegra.h
arch/arm/include/asm/arch-uniphier/platdevice.h [new file with mode: 0644]
arch/arm/include/asm/imx-common/mxc_i2c.h
arch/arm/include/asm/mach-types.h
arch/arm/include/asm/omap_gpio.h
arch/arm/include/asm/spl.h
arch/arm/include/asm/ti-common/keystone_nav.h [moved from arch/arm/include/asm/arch-keystone/keystone_nav.h with 91% similarity]
arch/arm/include/asm/ti-common/keystone_net.h [new file with mode: 0644]
arch/arm/include/asm/ti-common/keystone_serdes.h [new file with mode: 0644]
arch/arm/include/asm/ti-common/ti-edma3.h [new file with mode: 0644]
arch/arm/include/asm/u-boot-arm.h
arch/arm/lib/board.c
arch/arm/lib/bootm.c
arch/arm/lib/interrupts.c
arch/arm/mvebu-common/Makefile [new file with mode: 0644]
arch/arm/mvebu-common/dram.c [moved from arch/arm/cpu/arm926ejs/kirkwood/dram.c with 57% similarity]
arch/arm/mvebu-common/gpio.c [new file with mode: 0644]
arch/arm/mvebu-common/mbus.c [new file with mode: 0644]
arch/arm/mvebu-common/timer.c [moved from arch/arm/cpu/arm926ejs/kirkwood/timer.c with 63% similarity]
arch/mips/Kconfig
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/liodn.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/types.h
arch/sandbox/dts/sandbox.dts
arch/sandbox/include/asm/spi.h
arch/sandbox/include/asm/state.h
arch/x86/Kconfig
arch/x86/config.mk
arch/x86/cpu/Makefile
arch/x86/cpu/start.S
arch/x86/cpu/start16.S
arch/x86/dts/coreboot.dtsi
arch/x86/dts/link.dts
arch/x86/include/asm/arch-coreboot/gpio.h [new file with mode: 0644]
arch/x86/include/asm/bootm.h [new file with mode: 0644]
arch/x86/include/asm/config.h
arch/x86/include/asm/gpio.h
arch/x86/include/asm/ibmpc.h
arch/x86/lib/Makefile
arch/x86/lib/bootm.c
arch/x86/lib/zimage.c
board/8dtech/eco5pk/eco5pk.h
board/LaCie/net2big_v2/net2big_v2.c
board/LaCie/netspace_v2/netspace_v2.c
board/LaCie/wireless_space/wireless_space.c
board/Marvell/db-mv784mp-gp/Kconfig [new file with mode: 0644]
board/Marvell/db-mv784mp-gp/MAINTAINERS [new file with mode: 0644]
board/Marvell/db-mv784mp-gp/Makefile [new file with mode: 0644]
board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c [new file with mode: 0644]
board/Marvell/db-mv784mp-gp/kwbimage.cfg [new file with mode: 0644]
board/Marvell/dreamplug/dreamplug.c
board/Marvell/guruplug/guruplug.c
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
board/Marvell/openrd/openrd.c
board/Marvell/rd6281a/rd6281a.c
board/Marvell/sheevaplug/sheevaplug.c
board/Seagate/dockstar/dockstar.c
board/Seagate/goflexhome/goflexhome.c
board/atmel/at91rm9200ek/led.c
board/atmel/at91sam9260ek/led.c
board/buffalo/lsxl/lsxl.c
board/chromebook-x86/coreboot/Makefile
board/chromebook-x86/coreboot/coreboot.c [new file with mode: 0644]
board/cloudengines/pogo_e02/pogo_e02.c
board/compulab/cm_fx6/cm_fx6.c
board/compulab/cm_t35/cm_t35.c
board/d-link/dns325/dns325.c
board/freescale/ls1021aqds/MAINTAINERS
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1021atwr/MAINTAINERS
board/freescale/ls1021atwr/ls1021atwr.c
board/htkw/mcx/mcx.h
board/iomega/iconnect/iconnect.c
board/isee/igep00x0/igep00x0.c
board/karo/tk71/tk71.c
board/keymile/km_arm/km_arm.c
board/logicpd/am3517evm/am3517evm.h
board/logicpd/omap3som/omap3logic.c
board/logicpd/zoom1/zoom1.c
board/maxbcm/Kconfig [new file with mode: 0644]
board/maxbcm/MAINTAINERS [new file with mode: 0644]
board/maxbcm/Makefile [new file with mode: 0644]
board/maxbcm/kwbimage.cfg [new file with mode: 0644]
board/maxbcm/maxbcm.c [new file with mode: 0644]
board/nvidia/common/board.c
board/nvidia/common/emc.c
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
board/nvidia/seaboard/seaboard.c
board/overo/overo.c
board/overo/overo.h
board/pandora/pandora.h
board/raidsonic/ib62x0/ib62x0.c
board/raspberrypi/rpi_b/rpi_b.c
board/renesas/sh7752evb/sh7752evb.c
board/renesas/sh7753evb/sh7753evb.c
board/renesas/sh7757lcr/sh7757lcr.c
board/samsung/arndale/arndale.c
board/samsung/common/board.c
board/samsung/common/misc.c
board/samsung/goni/goni.c
board/samsung/origen/origen.c
board/samsung/smdk5250/exynos5-dt.c
board/samsung/smdk5420/smdk5420.c
board/samsung/smdkc100/smdkc100.c
board/samsung/smdkv310/smdkv310.c
board/samsung/trats/trats.c
board/samsung/trats2/trats2.c
board/samsung/universal_c210/universal.c
board/sunxi/Kconfig
board/sunxi/MAINTAINERS
board/sunxi/Makefile
board/sunxi/board.c
board/sunxi/dram_a20_olinuxino_l2.c [new file with mode: 0644]
board/technexion/tao3530/tao3530.h
board/technexion/twister/twister.c
board/technexion/twister/twister.h
board/teejet/mt_ventoux/mt_ventoux.h
board/ti/am335x/mux.c
board/ti/am3517crane/am3517crane.h
board/ti/beagle/beagle.c
board/ti/beagle/led.c
board/ti/evm/evm.h
board/ti/ks2_evm/Kconfig
board/ti/ks2_evm/MAINTAINERS
board/ti/ks2_evm/Makefile
board/ti/ks2_evm/board.c
board/ti/ks2_evm/board.h
board/ti/ks2_evm/board_k2e.c
board/ti/ks2_evm/board_k2hk.c
board/ti/ks2_evm/board_k2l.c [new file with mode: 0644]
board/ti/ks2_evm/ddr3_cfg.c
board/ti/ks2_evm/ddr3_cfg.h
board/ti/ks2_evm/ddr3_k2hk.c
board/ti/ks2_evm/ddr3_k2l.c [new file with mode: 0644]
board/ti/sdp3430/sdp.h
board/toradex/apalis_t30/Kconfig [new file with mode: 0644]
board/toradex/apalis_t30/MAINTAINERS [new file with mode: 0644]
board/toradex/apalis_t30/Makefile [new file with mode: 0644]
board/toradex/apalis_t30/apalis_t30.c [new file with mode: 0644]
board/toradex/apalis_t30/pinmux-config-apalis_t30.h [new file with mode: 0644]
board/toradex/colibri_t30/colibri_t30.c
board/w7o/fsboot.c
common/Makefile
common/board_f.c
common/board_r.c
common/bootm.c
common/cmd_blob.c [new file with mode: 0644]
common/cmd_bootm.c
common/cmd_elf.c
common/cmd_gpio.c
common/cmd_sf.c
common/cmd_spi.c
common/console.c
common/cros_ec.c
common/env_nand.c
common/env_sf.c
common/exports.c
common/image-fit.c
common/image.c
common/lcd.c
common/menu.c
common/modem.c
common/stdio.c
config.mk
configs/A10s-OLinuXino-M_defconfig
configs/A20-OLinuXino-Lime2_defconfig [new file with mode: 0644]
configs/A20-OLinuXino_MICRO_defconfig
configs/Colombus_defconfig [new file with mode: 0644]
configs/Ippo_q8h_defconfig [new file with mode: 0644]
configs/Mele_M3_defconfig [new file with mode: 0644]
configs/am335x_boneblack_defconfig
configs/am335x_boneblack_vboot_defconfig
configs/apalis_t30_defconfig [new file with mode: 0644]
configs/db-mv784mp-gp_defconfig [new file with mode: 0644]
configs/k2l_evm_defconfig [new file with mode: 0644]
configs/ls1021aqds_nor_SECURE_BOOT_defconfig [new file with mode: 0644]
configs/ls1021atwr_nor_SECURE_BOOT_defconfig [new file with mode: 0644]
configs/maxbcm_defconfig [new file with mode: 0644]
configs/ph1_ld4_defconfig
configs/ph1_pro4_defconfig
configs/ph1_sld8_defconfig
disk/part.c
doc/device-tree-bindings/mtd/spi/spi-flash.txt [new file with mode: 0644]
doc/device-tree-bindings/spi/soft-spi.txt [new file with mode: 0644]
doc/driver-model/README.txt
doc/driver-model/spi-howto.txt [new file with mode: 0644]
doc/uImage.FIT/kernel.its
doc/uImage.FIT/source_file_format.txt
doc/uImage.FIT/x86-fit-boot.txt [new file with mode: 0644]
drivers/Makefile
drivers/block/mvsata_ide.c
drivers/core/Kconfig
drivers/core/Makefile
drivers/core/device.c
drivers/core/lists.c
drivers/core/simple-bus.c [new file with mode: 0644]
drivers/core/uclass.c
drivers/crypto/Makefile
drivers/crypto/fsl/Makefile [new file with mode: 0644]
drivers/crypto/fsl/desc.h [new file with mode: 0644]
drivers/crypto/fsl/desc_constr.h [new file with mode: 0644]
drivers/crypto/fsl/error.c [new file with mode: 0644]
drivers/crypto/fsl/fsl_blob.c [new file with mode: 0644]
drivers/crypto/fsl/fsl_hash.c [new file with mode: 0644]
drivers/crypto/fsl/jobdesc.c [new file with mode: 0644]
drivers/crypto/fsl/jobdesc.h [new file with mode: 0644]
drivers/crypto/fsl/jr.c [new file with mode: 0644]
drivers/crypto/fsl/jr.h [new file with mode: 0644]
drivers/dfu/dfu_sf.c
drivers/dma/Makefile
drivers/dma/keystone_nav.c [moved from arch/arm/cpu/armv7/keystone/keystone_nav.c with 53% similarity]
drivers/dma/keystone_nav_cfg.c [new file with mode: 0644]
drivers/dma/ti-edma3.c [new file with mode: 0644]
drivers/gpio/Kconfig
drivers/gpio/bcm2835_gpio.c
drivers/gpio/gpio-uclass.c
drivers/gpio/intel_ich6_gpio.c
drivers/gpio/kw_gpio.c
drivers/gpio/mxc_gpio.c
drivers/gpio/omap_gpio.c
drivers/gpio/s5p_gpio.c
drivers/gpio/sandbox.c
drivers/gpio/tegra_gpio.c
drivers/i2c/designware_i2c.c
drivers/i2c/mvtwsi.c
drivers/i2c/tegra_i2c.c
drivers/input/tegra-kbc.c
drivers/misc/cros_ec.c
drivers/misc/cros_ec_lpc.c
drivers/misc/cros_ec_sandbox.c
drivers/misc/cros_ec_spi.c
drivers/mmc/bcm2835_sdhci.c
drivers/mmc/mvebu_mmc.c
drivers/mmc/omap_hsmmc.c
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
drivers/mmc/sunxi_mmc.c
drivers/mmc/tegra_mmc.c
drivers/mtd/cfi_flash.c
drivers/mtd/nand/kirkwood_nand.c
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/spi/Makefile
drivers/mtd/spi/ramtron.c
drivers/mtd/spi/sandbox.c
drivers/mtd/spi/sf-uclass.c [new file with mode: 0644]
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_params.c
drivers/mtd/spi/sf_probe.c
drivers/mtd/spi/spi_spl_load.c
drivers/net/Makefile
drivers/net/davinci_emac.c
drivers/net/fec_mxc.c
drivers/net/keystone_net.c
drivers/net/mvgbe.c
drivers/net/mvneta.c [new file with mode: 0644]
drivers/net/phy/phy.c
drivers/pci/pci.c
drivers/rtc/mvrtc.h
drivers/serial/Kconfig
drivers/serial/Makefile
drivers/serial/ns16550.c
drivers/serial/serial-uclass.c
drivers/serial/serial.c
drivers/serial/serial_coreboot.c [new file with mode: 0644]
drivers/serial/serial_mxc.c
drivers/serial/serial_ns16550.c
drivers/serial/serial_omap.c [new file with mode: 0644]
drivers/serial/serial_pl01x.c
drivers/serial/serial_pl01x_internal.h [moved from drivers/serial/serial_pl01x.h with 100% similarity]
drivers/serial/serial_s3c24x0.c
drivers/serial/serial_s5p.c
drivers/serial/serial_sh.c
drivers/serial/serial_uniphier.c
drivers/soc/Makefile [new file with mode: 0644]
drivers/soc/keystone/Makefile [new file with mode: 0644]
drivers/soc/keystone/keystone_serdes.c [new file with mode: 0644]
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/exynos_spi.c
drivers/spi/fdt_spi.c [deleted file]
drivers/spi/kirkwood_spi.c
drivers/spi/sandbox_spi.c
drivers/spi/soft_spi.c
drivers/spi/soft_spi_legacy.c [new file with mode: 0644]
drivers/spi/spi-emul-uclass.c [new file with mode: 0644]
drivers/spi/spi-uclass.c [new file with mode: 0644]
drivers/spi/tegra114_spi.c
drivers/spi/tegra20_sflash.c
drivers/spi/tegra20_slink.c
drivers/spi/tegra_spi.h [new file with mode: 0644]
drivers/usb/eth/asix.c
drivers/usb/host/Makefile
drivers/usb/host/dwc2.c [new file with mode: 0644]
drivers/usb/host/dwc2.h [new file with mode: 0644]
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci-marvell.c
drivers/usb/host/xhci-keystone.c [new file with mode: 0644]
drivers/video/cfb_console.c
drivers/video/exynos_fb.c
drivers/video/ipu_common.c
drivers/video/ipu_disp.c
drivers/video/mxc_ipuv3_fb.c
include/asm-generic/gpio.h
include/bootm.h
include/bootstage.h
include/common.h
include/config_fallbacks.h
include/configs/B4860QDS.h
include/configs/BSC9131RDB.h
include/configs/BSC9132QDS.h
include/configs/C29XPCIE.h
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240QDS.h
include/configs/T4240RDB.h
include/configs/am335x_evm.h
include/configs/am43xx_evm.h
include/configs/apalis_t30.h [new file with mode: 0644]
include/configs/cm_fx6.h
include/configs/colibri_t30.h
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/db-mv784mp-gp.h [new file with mode: 0644]
include/configs/edb93xx.h
include/configs/exynos-common.h
include/configs/k2e_evm.h
include/configs/k2hk_evm.h
include/configs/k2l_evm.h [new file with mode: 0644]
include/configs/ks2_evm.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls2085a_common.h
include/configs/maxbcm.h [new file with mode: 0644]
include/configs/omap3_overo.h
include/configs/peach-pit.h
include/configs/ph1_ld4.h
include/configs/ph1_pro4.h
include/configs/ph1_sld8.h
include/configs/rpi_b.h
include/configs/s5p_goni.h
include/configs/s5pc210_universal.h
include/configs/sacsng.h
include/configs/sandbox.h
include/configs/smdkc100.h
include/configs/socfpga_common.h
include/configs/socfpga_cyclone5.h
include/configs/sun4i.h
include/configs/sun5i.h
include/configs/sun6i.h [new file with mode: 0644]
include/configs/sun7i.h
include/configs/sun8i.h [new file with mode: 0644]
include/configs/sunxi-common.h
include/configs/tegra-common-post.h
include/configs/tegra-common.h
include/configs/ti_am335x_common.h
include/configs/ti_omap3_common.h
include/configs/tqma6.h
include/configs/uniphier-common.h
include/configs/zipitz2.h
include/cros_ec.h
include/dm/device-internal.h
include/dm/device.h
include/dm/lists.h
include/dm/platdata.h
include/dm/platform_data/serial-uniphier.h [new file with mode: 0644]
include/dm/platform_data/serial_mxc.h [new file with mode: 0644]
include/dm/platform_data/serial_pl01x.h [new file with mode: 0644]
include/dm/test.h
include/dm/uclass-id.h
include/dm/uclass.h
include/dm/util.h
include/dt-bindings/pinctrl/am33xx.h [moved from arch/arm/dts/dt-bindings/pinctrl/am33xx.h with 100% similarity]
include/dt-bindings/pinctrl/omap.h [moved from arch/arm/dts/dt-bindings/pinctrl/omap.h with 100% similarity]
include/elf.h
include/fdt_support.h
include/fdtdec.h
include/fsl_sec.h [new file with mode: 0644]
include/ide.h
include/image.h
include/libfdt.h
include/linker_lists.h
include/linux/mbus.h [new file with mode: 0644]
include/linux/string.h
include/linux/usb/dwc3.h
include/linux/usb/musb.h
include/mmc.h
include/netdev.h
include/ns16550.h
include/phy.h
include/spi.h
include/spi_flash.h
include/spl.h
include/usb.h
lib/Kconfig
lib/fdtdec.c
lib/initcall.c
lib/libfdt/fdt_ro.c
lib/lmb.c
lib/time.c
net/eth.c
net/tftp.c
post/post.c
scripts/Makefile.spl
scripts/multiconfig.sh
test/dm/Makefile
test/dm/bus.c
test/dm/core.c
test/dm/gpio.c
test/dm/sf.c [new file with mode: 0644]
test/dm/spi.c [new file with mode: 0644]
test/dm/test-dm.sh
test/dm/test-main.c
test/dm/test.dts
tools/Makefile
tools/kwbimage.c
tools/kwboot.c
tools/socfpgaimage.c

index 99097e1..26dacee 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -652,6 +652,10 @@ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
 libs-y += arch/$(ARCH)/imx-common/
 endif
 
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
+libs-y += arch/$(ARCH)/mvebu-common/
+endif
+
 libs-$(CONFIG_ARM) += arch/arm/cpu/
 libs-$(CONFIG_PPC) += arch/powerpc/cpu/
 
@@ -670,13 +674,9 @@ u-boot-main := $(libs-y)
 
 
 # Add GCC lib
-ifdef CONFIG_USE_PRIVATE_LIBGCC
 ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
 PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
 else
-PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
-endif
-else
 PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
@@ -754,6 +754,11 @@ endif
 endif
 endif
 
+# Add optional build target if defined in board/cpu/soc headers
+ifneq ($(CONFIG_BUILD_TARGET),)
+ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
+endif
+
 LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
diff --git a/README b/README
index 46def00..2808dd1 100644 (file)
--- a/README
+++ b/README
@@ -544,6 +544,12 @@ The following options need to be configured:
                CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
                Number of controllers used for other than main memory.
 
+               CONFIG_SYS_FSL_SEC_BE
+               Defines the SEC controller register space as Big Endian
+
+               CONFIG_SYS_FSL_SEC_LE
+               Defines the SEC controller register space as Little Endian
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -617,13 +623,6 @@ The following options need to be configured:
                exists, unlike the similar options in the Linux kernel. Do not
                set these options unless they apply!
 
-- CPU timer options:
-               CONFIG_SYS_HZ
-
-               The frequency of the timer returned by get_timer().
-               get_timer() must operate in milliseconds and this CONFIG
-               option must be set to 1000.
-
 - Linux Kernel Interface:
                CONFIG_CLOCKS_IN_MHZ
 
@@ -1459,6 +1458,9 @@ The following options need to be configured:
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.
 
+               CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
+               HW module registers.
+
 - USB Device:
                Define the below if you wish to use the USB console.
                Once firmware is rebuilt from a serial console issue the
@@ -2716,6 +2718,14 @@ CBFS (Coreboot Filesystem) support
                200 ms.
 
 - Configuration Management:
+               CONFIG_BUILD_TARGET
+
+               Some SoCs need special image types (e.g. U-Boot binary
+               with a special header) as build targets. By defining
+               CONFIG_BUILD_TARGET in the SoC / board header, this
+               special image will be automatically built upon calling
+               make / MAKEALL.
+
                CONFIG_IDENT_STRING
 
                If defined, this string will be added to the U-Boot
@@ -2824,10 +2834,6 @@ CBFS (Coreboot Filesystem) support
 
                Enable auto completion of commands using TAB.
 
-               Note that this feature has NOT been implemented yet
-               for the "hush" shell.
-
-
                CONFIG_SYS_HUSH_PARSER
 
                Define this variable to enable the "hush" shell (from
index bf26764..f63cc5a 100644 (file)
@@ -7,6 +7,7 @@ config ARC
 
 config ARM
        bool "ARM architecture"
+       select HAVE_PRIVATE_LIBGCC
        select SUPPORT_OF_CONTROL
 
 config AVR32
@@ -24,6 +25,7 @@ config MICROBLAZE
 
 config MIPS
        bool "MIPS architecture"
+       select HAVE_PRIVATE_LIBGCC
 
 config NDS32
        bool "NDS32 architecture"
@@ -36,6 +38,7 @@ config OPENRISC
 
 config PPC
        bool "PowerPC architecture"
+       select HAVE_PRIVATE_LIBGCC
 
 config SANDBOX
        bool "Sandbox"
@@ -43,12 +46,14 @@ config SANDBOX
 
 config SH
        bool "SuperH architecture"
+       select HAVE_PRIVATE_LIBGCC
 
 config SPARC
        bool "SPARC architecture"
 
 config X86
        bool "x86 architecture"
+       select HAVE_PRIVATE_LIBGCC
        select SUPPORT_OF_CONTROL
 
 endchoice
index 72558b8..8f910f3 100644 (file)
@@ -141,6 +141,12 @@ config ARCH_DAVINCI
 config KIRKWOOD
        bool "Marvell Kirkwood"
 
+config TARGET_DB_MV784MP_GP
+       bool "Support db-mv784mp-gp"
+
+config TARGET_MAXBCM
+       bool "Support maxbcm"
+
 config TARGET_DEVKIT3250
        bool "Support devkit3250"
 
@@ -444,9 +450,15 @@ config TARGET_SUN4I
 config TARGET_SUN5I
        bool "Support sun5i"
 
+config TARGET_SUN6I
+       bool "Support sun6i"
+
 config TARGET_SUN7I
        bool "Support sun7i"
 
+config TARGET_SUN8I
+       bool "Support sun8i"
+
 config TARGET_SNOWBALL
        bool "Support snowball"
 
@@ -567,6 +579,7 @@ source "board/BuS/eb_cpux9k2/Kconfig"
 source "board/BuS/vl_ma2sc/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/afeb9260/Kconfig"
@@ -648,6 +661,7 @@ source "board/jornada/Kconfig"
 source "board/karo/tx25/Kconfig"
 source "board/logicpd/imx27lite/Kconfig"
 source "board/logicpd/imx31_litekit/Kconfig"
+source "board/maxbcm/Kconfig"
 source "board/mpl/vcma9/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/palmld/Kconfig"
index 46ed055..b8d5c78 100644 (file)
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/arch/gpio.h>
+#include <status_led.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
index c230ce8..df4756e 100644 (file)
@@ -7,7 +7,5 @@
 #
 
 obj-y  = cpu.o
-obj-y  += dram.o
-obj-y  += mpp.o
-obj-y  += timer.o
 obj-y  += cache.o
+obj-y  += mpp.o
index 881e2de..9e412bb 100644 (file)
@@ -9,14 +9,11 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/cache.h>
-#include <u-boot/md5.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <mvebu_mmc.h>
 
-#define BUFLEN 16
-
 void reset_cpu(unsigned long ignored)
 {
        struct kwcpu_registers *cpureg =
@@ -29,31 +26,6 @@ void reset_cpu(unsigned long ignored)
        while (1) ;
 }
 
-/*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
-       int i;
-       u32 inbuf[BUFLEN];
-       u8 outbuf[BUFLEN];
-
-       /*
-        * in case of 88F6281/88F6282/88F6192 A0,
-        * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-        * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
-        * reserved regs and does not have names at this moment
-        * (no errata available)
-        */
-       writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
-       for (i = 0; i < BUFLEN; i++) {
-               inbuf[i] = readl(KW_REG_UNDOC_0x1470);
-       }
-       md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
-       return outbuf[outbuf[7] % 0x0f];
-}
-
 /*
  * Window Size
  * Used with the Base register to set the address window size and location.
@@ -139,50 +111,6 @@ int kw_config_adr_windows(void)
        return 0;
 }
 
-/*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
-       struct kwgpio_registers *gpio0reg =
-               (struct kwgpio_registers *)KW_GPIO0_BASE;
-       struct kwgpio_registers *gpio1reg =
-               (struct kwgpio_registers *)KW_GPIO1_BASE;
-
-       /* Init GPIOS to default values as per board requirement */
-       writel(gpp0_oe_val, &gpio0reg->dout);
-       writel(gpp1_oe_val, &gpio1reg->dout);
-       writel(gpp0_oe, &gpio0reg->oe);
-       writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
-               u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
-       u32 *mppreg = (u32 *) KW_MPP_BASE;
-
-       /* program mpp registers */
-       writel(mpp0_7, &mppreg[0]);
-       writel(mpp8_15, &mppreg[1]);
-       writel(mpp16_23, &mppreg[2]);
-       writel(mpp24_31, &mppreg[3]);
-       writel(mpp32_39, &mppreg[4]);
-       writel(mpp40_47, &mppreg[5]);
-       writel(mpp48_55, &mppreg[6]);
-       return 0;
-}
-
 /*
  * SYSRSTn Duration Counter Support
  *
index 0ba6f09..7222504 100644 (file)
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 
 static u32 kirkwood_variant(void)
index 828d10b..29b1d73 100644 (file)
@@ -9,7 +9,9 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
+#include <ns16550.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+       { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+       { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+       { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+       { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+       { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+       { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+       { "gpio_omap", &am33xx_gpio[0] },
+       { "gpio_omap", &am33xx_gpio[1] },
+       { "gpio_omap", &am33xx_gpio[2] },
+       { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+       { "gpio_omap", &am33xx_gpio[4] },
+       { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+
+# ifndef CONFIG_OF_CONTROL
+/*
+ * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
+ * the CONFIGs. At the same time, we should move this to the board files.
+ */
+static const struct ns16550_platdata am33xx_serial[] = {
+       { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
+#  ifdef CONFIG_SYS_NS16550_COM2
+       { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
+#   ifdef CONFIG_SYS_NS16550_COM3
+       { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
+       { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
+       { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
+       { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
+#   endif
+#  endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+       { "serial_omap", &am33xx_serial[0] },
+#  ifdef CONFIG_SYS_NS16550_COM2
+       { "serial_omap", &am33xx_serial[1] },
+#   ifdef CONFIG_SYS_NS16550_COM3
+       { "serial_omap", &am33xx_serial[2] },
+       { "serial_omap", &am33xx_serial[3] },
+       { "serial_omap", &am33xx_serial[4] },
+       { "serial_omap", &am33xx_serial[5] },
+#   endif
+#  endif
+};
+# endif
+
+#else
+
 static const struct gpio_bank gpio_bank_am33xx[] = {
        { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -49,6 +108,8 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 
+#endif
+
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int cpu_mmc_init(bd_t *bis)
 {
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile
new file mode 100644 (file)
index 0000000..885dcee
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  = cpu.o
diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c
new file mode 100644 (file)
index 0000000..1cf70a9
--- /dev/null
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define DDR_BASE_CS_OFF(n)     (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)     (0x0004 + ((n) << 3))
+
+static struct mbus_win windows[] = {
+       /* PCIE MEM address space */
+       { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+
+       /* PCIE IO address space */
+       { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+
+       /* SPI */
+       { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+         CPU_ATTR_SPIFLASH },
+
+       /* NOR */
+       { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+         CPU_ATTR_BOOTROM },
+};
+
+void reset_cpu(unsigned long ignored)
+{
+       struct mvebu_system_registers *reg =
+               (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
+
+       writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
+       writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
+       while (1)
+               ;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+       u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+
+       puts("SoC:   ");
+
+       switch (devid) {
+       case SOC_MV78460_ID:
+               puts("MV78460-");
+               break;
+       default:
+               puts("Unknown-");
+               break;
+       }
+
+       switch (revid) {
+       case 1:
+               puts("A0\n");
+               break;
+       case 2:
+               puts("B0\n");
+               break;
+       default:
+               puts("??\n");
+               break;
+       }
+
+       return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * This function initialize Controller DRAM Fastpath windows.
+ * It takes the CS size information from the 0x1500 scratch registers
+ * and sets the correct windows sizes and base addresses accordingly.
+ *
+ * These values are set in the scratch registers by the Marvell
+ * DDR3 training code, which is executed by the BootROM before the
+ * main payload (U-Boot) is executed. This training code is currently
+ * only available in the Marvell U-Boot version. It needs to be
+ * ported to mainline U-Boot SPL at some point.
+ */
+static void update_sdram_window_sizes(void)
+{
+       u64 base = 0;
+       u32 size, temp;
+       int i;
+
+       for (i = 0; i < SDRAM_MAX_CS; i++) {
+               size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
+               if (size != 0) {
+                       size |= ~(SDRAM_ADDR_MASK);
+
+                       /* Set Base Address */
+                       temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
+                       writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
+
+                       /*
+                        * Check if out of max window size and resize
+                        * the window
+                        */
+                       temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
+                               ~(SDRAM_ADDR_MASK)) | 1;
+                       temp |= (size & SDRAM_ADDR_MASK);
+                       writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
+
+                       base += ((u64)size + 1);
+               } else {
+                       /*
+                        * Disable window if not used, otherwise this
+                        * leads to overlapping enabled windows with
+                        * pretty strange results
+                        */
+                       clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
+               }
+       }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+       /* Linux expects the internal registers to be at 0xf1000000 */
+       writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+
+       /*
+        * We need to call mvebu_mbus_probe() before calling
+        * update_sdram_window_sizes() as it disables all previously
+        * configured mbus windows and then configures them as
+        * required for U-Boot. Calling update_sdram_window_sizes()
+        * without this configuration will not work, as the internal
+        * registers can't be accessed reliably because of potenial
+        * double mapping.
+        * After updating the SDRAM access windows we need to call
+        * mvebu_mbus_probe() again, as this now correctly configures
+        * the SDRAM areas that are later used by the MVEBU drivers
+        * (e.g. USB, NETA).
+        */
+
+       /*
+        * First disable all windows
+        */
+       mvebu_mbus_probe(NULL, 0);
+
+       /*
+        * Now the SDRAM access windows can be reconfigured using
+        * the information in the SDRAM scratch pad registers
+        */
+       update_sdram_window_sizes();
+
+       /*
+        * Finally the mbus windows can be configured with the
+        * updated SDRAM sizes
+        */
+       mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+
+       return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+       /* Nothing yet, perhaps we need something here later */
+       return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVNETA
+int cpu_eth_init(bd_t *bis)
+{
+       mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
+       mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
+       mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
+       mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+
+       return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif
index b929486..3d95dc3 100644 (file)
@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
 
@@ -172,6 +172,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
                 * this same assumption.
                 */
                if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
+#ifndef CONFIG_SPL_BUILD
+                       gpio_request(i, "sdmmc0_vdden");
+#endif
                        gpio_set_value(i, 1);
                        gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
                } else {
index 8249b5e..393885f 100644 (file)
@@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
 config TARGET_K2E_EVM
        bool "TI Keystone 2 Edison EVM"
 
+config TARGET_K2L_EVM
+       bool "TI Keystone 2 Lamar EVM"
+
 endchoice
 
 config SYS_CPU
index f8519c0..ed030db 100644 (file)
@@ -10,10 +10,9 @@ obj-y        += psc.o
 obj-y  += clock.o
 obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
 obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y  += msmc.o
-obj-$(CONFIG_SPL_BUILD)        += spl.o
-obj-y  += ddr3.o
+obj-y  += ddr3.o cmd_ddr3.o
 obj-y  += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644 (file)
index 0000000..1c5e4d5
--- /dev/null
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+       [TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
+       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+       SPD800,
+       SPD1000,
+       SPD1200,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD1200,
+       SPD1000,
+       SPD800,
+       SPD800,
+       SPD800,
+};
+
+int arm_speeds[] = {
+       SPD800,
+       SPD1000,
+       SPD1200,
+       SPD1350,
+       SPD1400,
+       SPD800,
+       SPD1400,
+       SPD1350,
+       SPD1200,
+       SPD1000,
+       SPD800,
+       SPD800,
+       SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:       pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+       unsigned long mult = 1, prediv = 1, output_div = 2;
+       unsigned long ret;
+       u32 tmp, reg;
+
+       if (pll == CORE_PLL) {
+               ret = external_clk[sys_clk];
+               if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+                       /* PLL mode */
+                       tmp = __raw_readl(KS2_MAINPLLCTL0);
+                       prediv = (tmp & PLL_DIV_MASK) + 1;
+                       mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+                               (pllctl_reg_read(pll, mult) &
+                               PLLM_MULT_LO_MASK)) + 1;
+                       output_div = ((pllctl_reg_read(pll, secctl) >>
+                                       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+                       ret = ret / prediv / output_div * mult;
+               }
+       } else {
+               switch (pll) {
+               case PASS_PLL:
+                       ret = external_clk[pa_clk];
+                       reg = KS2_PASSPLLCTL0;
+                       break;
+               case TETRIS_PLL:
+                       ret = external_clk[tetris_clk];
+                       reg = KS2_ARMPLLCTL0;
+                       break;
+               case DDR3_PLL:
+                       ret = external_clk[ddr3_clk];
+                       reg = KS2_DDR3APLLCTL0;
+                       break;
+               default:
+                       return 0;
+               }
+
+               tmp = __raw_readl(reg);
+               if (!(tmp & PLLCTL_BYPASS)) {
+                       /* Bypass disabled */
+                       prediv = (tmp & PLL_DIV_MASK) + 1;
+                       mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+                       output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+                                     PLL_CLKOD_MASK) + 1;
+                       ret = ((ret / prediv) * mult) / output_div;
+               }
+       }
+
+       return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+       switch (clk) {
+       case core_pll_clk:      return pll_freq_get(CORE_PLL);
+       case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+       case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
+       case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+       case sys_clk0_1_clk:
+       case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+       case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+       case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+       case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+       case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+       case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+       case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+       case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+       case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+       case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+       case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+       case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+       case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+       case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+       case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+       default:
+               break;
+       }
+
+       return 0;
+}
index 47fc893..d13fbc1 100644 (file)
@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
                tmp &= ~(PLL_BWADJ_HI_MASK);
                tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
-               /* set PLL Select (bit 13) for PASS PLL */
-               if (data->pll == PASS_PLL)
-                       tmp |= PLLCTL_PAPLL;
-
                __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
                /* Reset bit: bit 14 for both DDR3 & PASS PLL */
@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
        return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
 }
 #endif
+
+void pass_pll_pa_clk_enable(void)
+{
+       u32 reg;
+
+       reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+       reg |= PLLCTL_PAPLL;
+       writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+       /* wait till clock is enabled */
+       sdelay(15000);
+}
index d97c95b..af1b701 100644 (file)
@@ -58,20 +58,11 @@ pll_cmd_usage:
        return cmd_usage(cmdtp);
 }
 
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
-       pllset, 5,      0,      do_pll_cmd,
-       "set pll multiplier and pre divider",
-       "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
-);
-#endif
-#ifdef CONFIG_SOC_K2E
 U_BOOT_CMD(
        pllset, 5,      0,      do_pll_cmd,
        "set pll multiplier and pre divider",
-       "<pa|ddr3> <mult> <div> <OD>\n"
+       PLLSET_CMD_LIST " <mult> <div> <OD>\n"
 );
-#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -95,12 +86,8 @@ U_BOOT_CMD(
        getclk, 2,      0,      do_getclk_cmd,
        "get clock rate",
        "<clk index>\n"
-#ifdef CONFIG_SOC_K2HK
-       "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
-#endif
-#ifdef CONFIG_SOC_K2E
-       "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
-#endif
+       "The indexes for clocks:\n"
+       CLOCK_INDEXES_LIST
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -141,5 +128,8 @@ U_BOOT_CMD(
        psc,    3,      0,      do_psc_cmd,
        "<enable/disable psc module os disable domain>",
        "<mod/domain index> <en|di|domain>\n"
-       "See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+       "Intended to control Power and Sleep Controller (PSC) domains and\n"
+       "modules. The module or domain index exectly corresponds to ones\n"
+       "listed in official TRM. For instance, to enable MSMC RAM clock\n"
+       "domain use command: psc 14 en.\n"
 );
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
new file mode 100644 (file)
index 0000000..ea78ad8
--- /dev/null
@@ -0,0 +1,248 @@
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr3.h>
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR           CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR         0x80000000
+#define ECC_START_ADDR1                ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
+
+#define ECC_END_ADDR1          (((gd->start_addr_sp - DDR_REMAP_ADDR - \
+                                CONFIG_STACKSIZE) >> 17) - 2)
+
+#define DDR_TEST_BURST_SIZE    1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+       u32 index_start, value, index;
+
+       index_start = start_address;
+
+       while (1) {
+               /* Write a pattern */
+               for (index = index_start;
+                               index < index_start + DDR_TEST_BURST_SIZE;
+                               index += 4)
+                       __raw_writel(index, index);
+
+               /* Read and check the pattern */
+               for (index = index_start;
+                               index < index_start + DDR_TEST_BURST_SIZE;
+                               index += 4) {
+                       value = __raw_readl(index);
+                       if (value != index) {
+                               printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+                                      index, value, __raw_readl(index));
+
+                               return -1;
+                       }
+               }
+
+               index_start += DDR_TEST_BURST_SIZE;
+               if (index_start >= end_address)
+                       break;
+
+               if (quick)
+                       continue;
+
+               /* Write a pattern for complementary values */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 4)
+                       __raw_writel((u32)~index, index);
+
+               /* Read and check the pattern */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 4) {
+                       value = __raw_readl(index);
+                       if (value != ~index) {
+                               printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+                                      index, value, __raw_readl(index));
+
+                               return -1;
+                       }
+               }
+
+               index_start += DDR_TEST_BURST_SIZE;
+               if (index_start >= end_address)
+                       break;
+
+               /* Write a pattern */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 2)
+                       __raw_writew((u16)index, index);
+
+               /* Read and check the pattern */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 2) {
+                       value = __raw_readw(index);
+                       if (value != (u16)index) {
+                               printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+                                      index, value, __raw_readw(index));
+
+                               return -1;
+                       }
+               }
+
+               index_start += DDR_TEST_BURST_SIZE;
+               if (index_start >= end_address)
+                       break;
+
+               /* Write a pattern */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 1)
+                       __raw_writeb((u8)index, index);
+
+               /* Read and check the pattern */
+               for (index = index_start;
+                    index < index_start + DDR_TEST_BURST_SIZE;
+                    index += 1) {
+                       value = __raw_readb(index);
+                       if (value != (u8)index) {
+                               printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+                                      index, value, __raw_readb(index));
+
+                               return -1;
+                       }
+               }
+
+               index_start += DDR_TEST_BURST_SIZE;
+               if (index_start >= end_address)
+                       break;
+       }
+
+       puts("ddr memory test PASSED!\n");
+       return 0;
+}
+
+static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
+{
+       u32 index, value, index2, value2;
+
+       for (index = address1, index2 = address2;
+            index < address1 + size;
+            index += 4, index2 += 4) {
+               value = __raw_readl(index);
+               value2 = __raw_readl(index2);
+
+               if (value != value2) {
+                       printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
+                              index, value, index2, value2);
+
+                       return -1;
+               }
+       }
+
+       puts("ddr memory compare PASSED!\n");
+       return 0;
+}
+
+static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
+{
+       u32 value1, value2, value3;
+
+       puts("Disabling DDR ECC ...\n");
+       ddr3_disable_ecc(base);
+
+       value1 = __raw_readl(address);
+       value2 = value1 ^ ecc_err;
+       __raw_writel(value2, address);
+
+       value3 = __raw_readl(address);
+       printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+              address, value1, value2, ecc_err, value3);
+
+       __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
+                    base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+       puts("Enabling DDR ECC ...\n");
+       ddr3_enable_ecc(base, 1);
+
+       value1 = __raw_readl(address);
+       printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
+
+       ddr3_check_ecc_int(base);
+       return 0;
+}
+
+static int do_ddr_test(cmd_tbl_t *cmdtp,
+                      int flag, int argc, char * const argv[])
+{
+       u32 start_addr, end_addr, size, ecc_err;
+
+       if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
+               if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
+                       puts("ECC RMW isn't supported for this SOC\n");
+                       return 1;
+               }
+
+               start_addr = simple_strtoul(argv[2], NULL, 16);
+               ecc_err = simple_strtoul(argv[3], NULL, 16);
+
+               if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+                   (start_addr > (CONFIG_SYS_SDRAM_BASE +
+                    CONFIG_MAX_RAM_BANK_SIZE - 1))) {
+                       puts("Invalid address!\n");
+                       return cmd_usage(cmdtp);
+               }
+
+               ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
+                                  start_addr, ecc_err);
+               return 0;
+       }
+
+       if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
+             ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
+               return cmd_usage(cmdtp);
+
+       start_addr = simple_strtoul(argv[2], NULL, 16);
+       end_addr = simple_strtoul(argv[3], NULL, 16);
+
+       if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+           (start_addr > (CONFIG_SYS_SDRAM_BASE +
+            CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
+           (end_addr < CONFIG_SYS_SDRAM_BASE) ||
+           (end_addr > (CONFIG_SYS_SDRAM_BASE +
+            CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
+               puts("Invalid start or end address!\n");
+               return cmd_usage(cmdtp);
+       }
+
+       puts("Please wait ...\n");
+       if (argc == 5) {
+               size = simple_strtoul(argv[4], NULL, 16);
+               ddr_memory_compare(start_addr, end_addr, size);
+       } else {
+               ddr_memory_test(start_addr, end_addr, 0);
+       }
+
+       return 0;
+}
+
+U_BOOT_CMD(ddr,        5, 1, do_ddr_test,
+          "DDR3 test",
+          "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
+          "    address to end address\n"
+          "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
+          "    compare DDR data of (size) bytes from start address to end\n"
+          "    address\n"
+          "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
+          "    in DDR data at <addr>, the command will read a 32-bit data\n"
+          "    from <addr>, and write (data ^ bit_err) back to <addr>\n"
+);
index 2eabec1..923906a 100644 (file)
@@ -9,9 +9,19 @@
 
 #include <asm/io.h>
 #include <common.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
 
+#include <asm/ti-common/ti-edma3.h>
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT       10
+#define DDR3_EDMA_BLK_SIZE             (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT                 0x8000
+#define DDR3_EDMA_CCNT                 1
+#define DDR3_EDMA_XF_SIZE              (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM             1
+
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
        unsigned int tmp;
@@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
        __raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
 
+int ddr3_ecc_support_rmw(u32 base)
+{
+       u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+       /* Check the DDR3 controller ID reg if the controllers
+          supports ECC RMW or not */
+       if (value == 0x40461C02)
+               return 1;
+
+       return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+       u32 data;
+
+       __raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);
+       udelay(100000); /* delay required to synchronize across clock domains */
+
+       if (value & KS2_DDR3_ECC_EN) {
+               /* Clear the 1-bit error count */
+               data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+               __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+               /* enable the ECC interrupt */
+               __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+                            KS2_DDR3_WR_ECC_ERR_SYS,
+                            base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+               /* Clear the ECC error interrupt status */
+               __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+                            KS2_DDR3_WR_ECC_ERR_SYS,
+                            base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+       }
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+       u32 mpax[2];
+       u32 seg_num;
+       u32 seg, blks, dst, edma_blks;
+       struct edma3_slot_config slot;
+       struct edma3_channel_config edma_channel;
+       u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+       /* Setup an edma to copy the 1k block to the entire DDR */
+       puts("\nClear entire DDR3 memory to enable ECC\n");
+
+       /* save the SES MPAX regs */
+       msmc_get_ses_mpax(8, 0, mpax);
+
+       /* setup edma slot 1 configuration */
+       slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+                  EDMA3_SLOPT_COMP_CODE(0) |
+                  EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+       slot.bcnt = DDR3_EDMA_BCNT;
+       slot.acnt = DDR3_EDMA_BLK_SIZE;
+       slot.ccnt = DDR3_EDMA_CCNT;
+       slot.src_bidx = 0;
+       slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+       slot.src_cidx = 0;
+       slot.dst_cidx = 0;
+       slot.link = EDMA3_PARSET_NULL_LINK;
+       slot.bcntrld = 0;
+       edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
+
+       /* configure quik edma channel */
+       edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+       edma_channel.chnum = 0;
+       edma_channel.complete_code = 0;
+       /* event trigger after dst update */
+       edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+       qedma3_start(KS2_EDMA0_BASE, &edma_channel);
+
+       /* DDR3 size in segments (4KB seg size) */
+       seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
+
+       for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
+               /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
+                  access slave interface so that edma driver can access */
+               msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
+                                    KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+
+               if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
+                       edma_blks = KS2_MSMC_MAP_SEG_NUM <<
+                                       (KS2_MSMC_SEG_SIZE_SHIFT
+                                       - DDR3_EDMA_BLK_SIZE_SHIFT);
+               else
+                       edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
+                                       - DDR3_EDMA_BLK_SIZE_SHIFT);
+
+               /* Use edma driver to scrub 2GB DDR memory */
+               for (dst = base, blks = 0; blks < edma_blks;
+                    blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
+                       edma3_set_src_addr(KS2_EDMA0_BASE,
+                                          edma_channel.slot, (u32)edma_src);
+                       edma3_set_dest_addr(KS2_EDMA0_BASE,
+                                           edma_channel.slot, (u32)dst);
+
+                       while (edma3_check_for_transfer(KS2_EDMA0_BASE,
+                                                       &edma_channel))
+                               udelay(10);
+               }
+       }
+
+       qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
+
+       /* restore the SES MPAX regs */
+       msmc_set_ses_mpax(8, 0, mpax);
+}
+
+static void ddr3_ecc_init_range(u32 base)
+{
+       u32 ecc_val = KS2_DDR3_ECC_EN;
+       u32 rmw = ddr3_ecc_support_rmw(base);
+
+       if (rmw)
+               ecc_val |= KS2_DDR3_ECC_RMW_EN;
+
+       __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+       ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_enable_ecc(u32 base, int test)
+{
+       u32 ecc_val = KS2_DDR3_ECC_ENABLE;
+       u32 rmw = ddr3_ecc_support_rmw(base);
+
+       if (test)
+               ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
+
+       if (!rmw) {
+               if (!test)
+                       /* by default, disable ecc when rmw = 0 and no
+                          ecc test */
+                       ecc_val = 0;
+       } else {
+               ecc_val |= KS2_DDR3_ECC_RMW_EN;
+       }
+
+       ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_disable_ecc(u32 base)
+{
+       ddr3_ecc_config(base, 0);
+}
+
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+static void cic_init(u32 base)
+{
+       /* Disable CIC global interrupts */
+       __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
+
+       /* Set to normal mode, no nesting, no priority hold */
+       __raw_writel(0, base + KS2_CIC_CTRL);
+       __raw_writel(0, base + KS2_CIC_HOST_CTRL);
+
+       /* Enable CIC global interrupts */
+       __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
+}
+
+static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
+{
+       /* Map the system interrupt to a CIC channel */
+       __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
+
+       /* Enable CIC system interrupt */
+       __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
+
+       /* Enable CIC Host interrupt */
+       __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
+}
+
+static void ddr3_map_ecc_cic2_irq(u32 base)
+{
+       cic_init(base);
+       cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
+                          KS2_CIC2_DDR3_ECC_IRQ_NUM);
+}
+#endif
+
+void ddr3_init_ecc(u32 base)
+{
+       u32 ddr3_size;
+
+       if (!ddr3_ecc_support_rmw(base)) {
+               ddr3_disable_ecc(base);
+               return;
+       }
+
+       ddr3_ecc_init_range(base);
+       ddr3_size = ddr3_get_size();
+       ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+
+       /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+       ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
+#endif
+       ddr3_enable_ecc(base, 0);
+}
+
+void ddr3_check_ecc_int(u32 base)
+{
+       char *env;
+       int ecc_test = 0;
+       u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+
+       env = getenv("ecc_test");
+       if (env)
+               ecc_test = simple_strtol(env, NULL, 0);
+
+       if (value & KS2_DDR3_WR_ECC_ERR_SYS)
+               puts("DDR3 ECC write error interrupted\n");
+
+       if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
+               puts("DDR3 ECC 2-bit error interrupted\n");
+
+               if (!ecc_test) {
+                       puts("Reseting the device ...\n");
+                       reset_cpu(0);
+               }
+       }
+
+       value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+       if (value) {
+               printf("1-bit ECC err count: 0x%x\n", value);
+               value = __raw_readl(base +
+                                   KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
+               printf("1-bit ECC err address log: 0x%x\n", value);
+       }
+}
+
 void ddr3_reset_ddrphy(void)
 {
        u32 tmp;
index a8f8aee..c2b9478 100644 (file)
@@ -13,6 +13,7 @@
 #include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
 
 void chip_configuration_unlock(void)
 {
@@ -20,17 +21,67 @@ void chip_configuration_unlock(void)
        __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+       u32 i;
+       u32 j;
+       u32 val;
+       u32 base = KS2_OSR_CFG_BASE;
+       u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+       /* Enable the OSR clock domain */
+       psc_enable_module(KS2_LPSC_OSR);
+
+       /* Disable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+               val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+                       (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+               writel(val , base + KS2_OSR_ECC_VEC);
+
+               /**
+                * wait till read is done.
+                * Print should be added after earlyprintk support is added.
+                */
+               for (j = 0; j < 10000; j++) {
+                       val = readl(base + KS2_OSR_ECC_VEC);
+                       if (val & KS2_OSR_ECC_VEC_RD_DONE)
+                               break;
+               }
+
+               ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+                                               KS2_OSR_ECC_CTRL_CHK;
+
+               writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+               writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+       }
+
+       /* Reset OSR memory to all zeros */
+       for (i = 0; i < KS2_OSR_SIZE; i += 4)
+               writel(0, KS2_OSR_DATA_BASE + i);
+
+       /* Enable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+               writel(ecc_ctrl[i] |
+                      KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
 int arch_cpu_init(void)
 {
        chip_configuration_unlock();
        icache_enable();
 
-       msmc_share_all_segments(8);  /* TETRIS */
-       msmc_share_all_segments(9);  /* NETCP */
-       msmc_share_all_segments(10); /* QM PDSP */
-       msmc_share_all_segments(11); /* PCIE 0 */
-#ifdef CONFIG_SOC_K2E
-       msmc_share_all_segments(13); /* PCIE 1 */
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+#endif
+#ifdef CONFIG_SOC_K2L
+       osr_init();
 #endif
 
        /*
index 7d8e597..7899141 100644 (file)
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
                msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
        }
 }
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+                         u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+       struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+       msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
+                                            (size & 0x1f) | 0x80;
+       msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+       struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+       *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
+       *mpax = msmc->ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+       struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+       msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
+       msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644 (file)
index d4b0e9b..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spl.h>
-#include <spi_flash.h>
-
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
-       CORE_PLL_799,
-       TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
-       CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
-       init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
-       spl_init_keystone_plls();
-       preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
-       return BOOT_DEVICE_SPI;
-#else
-       puts("Unknown boot device\n");
-       hang();
-#endif
-}
index 6dc2600..dd5aaa2 100644 (file)
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <asm/armv7.h>
+#include <asm/bootm.h>
 #include <asm/pl310.h>
 #include <asm/errno.h>
 #include <asm/io.h>
index 6fae1e5..4a48f84 100644 (file)
@@ -16,7 +16,7 @@ config TARGET_OMAP3_BEAGLE
        bool "TI OMAP3 BeagleBoard"
 
 config TARGET_CM_T35
-       bool "CompuLab CM-T35"
+       bool "CompuLab CM-T3530 and CM-T3730 boards"
 
 config TARGET_DEVKIT8000
        bool "TimLL OMAP3 Devkit8000"
index 667e77f..c942fe6 100644 (file)
  * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <mmc.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
@@ -38,6 +40,27 @@ static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 #endif
 
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata omap34xx_gpio[] = {
+       { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+       { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+       { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+       { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+       { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+       { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+       { "gpio_omap", &omap34xx_gpio[0] },
+       { "gpio_omap", &omap34xx_gpio[1] },
+       { "gpio_omap", &omap34xx_gpio[2] },
+       { "gpio_omap", &omap34xx_gpio[3] },
+       { "gpio_omap", &omap34xx_gpio[4] },
+       { "gpio_omap", &omap34xx_gpio[5] },
+};
+
+#else
+
 static const struct gpio_bank gpio_bank_34xx[6] = {
        { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
        { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
@@ -49,6 +72,8 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 /*
 * We use static variables because global data is not ready yet.
@@ -266,7 +291,7 @@ int __weak misc_init_r(void)
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
  *****************************************************************************/
-void wait_for_command_complete(struct watchdog *wd_base)
+static void wait_for_command_complete(struct watchdog *wd_base)
 {
        int pending = 1;
        do {
index 6c7330a..a2aadc9 100644 (file)
@@ -61,7 +61,7 @@ u32 get_sdr_cs_offset(u32 cs)
  *  - Init the emif4 module for DDR access
  *  - Early init routines, called from flash or SRAM.
  */
-void do_emif4_init(void)
+static void do_emif4_init(void)
 {
        unsigned int regval;
        /* Set the DDR PHY parameters in PHY ctrl registers */
index bef5f05..bbb65bb 100644 (file)
@@ -16,6 +16,8 @@
 #include <asm/io.h>
 #include <asm/arch/mem.h>      /* get mem tables */
 #include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+
 #include <i2c.h>
 #include <linux/compiler.h>
 
@@ -202,7 +204,7 @@ u32 __weak get_board_rev(void)
 /********************************************************
  *  get_base(); get upper addr of current execution
  *******************************************************/
-u32 get_base(void)
+static u32 get_base(void)
 {
        u32 val;
 
index 0eab264..8c3e5f7 100644 (file)
@@ -176,7 +176,7 @@ static void socfpga_nic301_slave_ns(void)
 
 static uint32_t iswgrp_handoff[8];
 
-int misc_init_r(void)
+int arch_early_init_r(void)
 {
        int i;
        for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
index db9bdad..569fa41 100644 (file)
@@ -42,13 +42,4 @@ SECTIONS
                . = ALIGN(4);
                __bss_end = .;
        } >.sdram
-
-       . = ALIGN(8);
-       __malloc_start = .;
-       . = . + CONFIG_SPL_MALLOC_SIZE;
-       __malloc_end = .;
-
-       . = . + CONFIG_SPL_STACK_SIZE;
-       . = ALIGN(8);
-       __stack_start = .;
 }
index e9721b2..24f1dae 100644 (file)
@@ -11,9 +11,13 @@ obj-y        += timer.o
 obj-y  += board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
+obj-$(CONFIG_SUN6I)    += prcm.o
+obj-$(CONFIG_SUN8I)    += prcm.o
 obj-$(CONFIG_SUN4I)    += clock_sun4i.o
 obj-$(CONFIG_SUN5I)    += clock_sun4i.o
+obj-$(CONFIG_SUN6I)    += clock_sun6i.o
 obj-$(CONFIG_SUN7I)    += clock_sun4i.o
+obj-$(CONFIG_SUN8I)    += clock_sun6i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y  += cpu_info.o
index f2cedbb..06eb676 100644 (file)
@@ -50,18 +50,35 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+       /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+       sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+       sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+       sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
-       sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+       sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-       sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+       sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+       sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+       sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+       sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
        sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
        sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-       sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+       sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+       sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
@@ -71,6 +88,7 @@ int gpio_init(void)
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
        static const struct sunxi_wdog *wdog =
                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -82,12 +100,22 @@ void reset_cpu(ulong addr)
                /* sun5i sometimes gets stuck without this */
                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
        }
+#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
+       static const struct sunxi_wdog *wdog =
+                ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+       /* Set the watchdog for its shortest interval (.5s) and wait */
+       writel(WDT_CFG_RESET, &wdog->cfg);
+       writel(WDT_MODE_EN, &wdog->mode);
+       writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+#endif
 }
 
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
+               defined CONFIG_SUN6I || defined CONFIG_SUN8I)
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
        asm volatile(
                "mrc p15, 0, r0, c1, c0, 1\n"
index ecbdb01..4a0d64f 100644 (file)
@@ -180,6 +180,17 @@ void clock_set_pll1(unsigned int hz)
 }
 #endif
 
+unsigned int clock_get_pll5p(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll5_cfg);
+       int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+       int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+       int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+       return (24000000 * n * k) >> p;
+}
+
 unsigned int clock_get_pll6(void)
 {
        struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
new file mode 100644 (file)
index 0000000..1eae976
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if CONFIG_CONS_INDEX < 5
+       /* uart clock source is apb2 */
+       writel(APB2_CLK_SRC_OSC24M|
+              APB2_CLK_RATE_N_1|
+              APB2_CLK_RATE_M(1),
+              &ccm->apb2_div);
+
+       /* open the clock for uart */
+       setbits_le32(&ccm->apb2_gate,
+                    CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+                                      CONFIG_CONS_INDEX - 1));
+
+       /* deassert uart reset */
+       setbits_le32(&ccm->apb2_reset_cfg,
+                    1 << (APB2_RESET_UART_SHIFT +
+                          CONFIG_CONS_INDEX - 1));
+#else
+       /* enable R_PIO and R_UART clocks, and de-assert resets */
+       prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
+
+       /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       if (port > 3)
+               return -1;
+
+       /* set the apb clock gate for twi */
+       if (state)
+               setbits_le32(&ccm->apb2_gate,
+                            CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+       else
+               clrbits_le32(&ccm->apb2_gate,
+                            CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+       return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll6_cfg);
+       int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+       int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+       return 24000000 * n * k / 2;
+}
index 5cf35ac..4f2a09c 100644 (file)
@@ -23,8 +23,12 @@ int print_cpuinfo(void)
        case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
        default: puts("CPU:   Allwinner A1X (SUN5I)\n");
        }
+#elif defined CONFIG_SUN6I
+       puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
        puts("CPU:   Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_SUN8I
+       puts("CPU:   Allwinner A23 (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
        puts("CPU:   SUNXI Family\n");
index 584f742..3cf3cbf 100644 (file)
@@ -252,15 +252,9 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 {
        u32 reg_val;
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-       /* PLL5P and PLL6 are the potential clock sources for MBUS */
-       u32 pll6x_div, pll5p_div;
-       u32 pll6x_clk = clock_get_pll6() / 1000000;
-       u32 pll5p_clk = clk / 24 * 48;
+       u32 pll5p_clk, pll6x_clk;
+       u32 pll5p_div, pll6x_div;
        u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
-       pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
 
        /* setup DRAM PLL */
        reg_val = readl(&ccm->pll5_cfg);
@@ -268,33 +262,32 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
        reg_val &= ~CCM_PLL5_CTRL_K_MASK;               /* set K to 0 (x1) */
        reg_val &= ~CCM_PLL5_CTRL_N_MASK;               /* set N to 0 (x0) */
        reg_val &= ~CCM_PLL5_CTRL_P_MASK;               /* set P to 0 (x1) */
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+       /* Old kernels are hardcoded to P=1 (divide by 2) */
+       reg_val |= CCM_PLL5_CTRL_P(1);
+#endif
        if (clk >= 540 && clk < 552) {
-               /* dram = 540MHz, pll5p = 1080MHz */
-               pll5p_clk = 1080;
+               /* dram = 540MHz */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
        } else if (clk >= 512 && clk < 528) {
-               /* dram = 512MHz, pll5p = 1536MHz */
-               pll5p_clk = 1536;
+               /* dram = 512MHz */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
        } else if (clk >= 496 && clk < 504) {
-               /* dram = 496MHz, pll5p = 1488MHz */
-               pll5p_clk = 1488;
+               /* dram = 496MHz */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
        } else if (clk >= 468 && clk < 480) {
-               /* dram = 468MHz, pll5p = 936MHz */
-               pll5p_clk = 936;
+               /* dram = 468MHz */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
        } else if (clk >= 396 && clk < 408) {
-               /* dram = 396MHz, pll5p = 792MHz */
-               pll5p_clk = 792;
+               /* dram = 396MHz */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
@@ -322,6 +315,13 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
        /* setup MBUS clock */
        if (!mbus_clk)
                mbus_clk = 300;
+
+       /* PLL5P and PLL6 are the potential clock sources for MBUS */
+       pll6x_clk = clock_get_pll6() / 1000000;
+#ifdef CONFIG_SUN7I
+       pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+       pll5p_clk = clock_get_pll5p() / 1000000;
        pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
        pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
        pll6x_rate = pll6x_clk / pll6x_div;
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644 (file)
index 0000000..19b4938
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
+{
+       struct sunxi_prcm_reg *prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+       /* open the clock for module */
+       setbits_le32(&prcm->apb0_gate, flags);
+
+       /* deassert reset for module */
+       setbits_le32(&prcm->apb0_reset, flags);
+}
index bcae2d6..3ea6d76 100644 (file)
@@ -17,6 +17,9 @@ config TEGRA124
 
 endchoice
 
+config USE_PRIVATE_LIBGCC
+       default y if SPL_BUILD
+
 config SYS_CPU
        default "arm720t" if SPL_BUILD
        default "armv7" if !SPL_BUILD
index fd77f3f..d98cec9 100644 (file)
@@ -194,7 +194,8 @@ static void rgb_enable(struct dc_com_reg *com)
                writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
 }
 
-int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+static int setup_window(struct disp_ctl_win *win,
+                       struct fdt_disp_config *config)
 {
        win->x = 0;
        win->y = 0;
index 54aec4e..3abdc7b 100644 (file)
@@ -3,6 +3,9 @@ if TEGRA30
 choice
        prompt "Tegra30 board select"
 
+config TARGET_APALIS_T30
+       bool "Toradex Apalis T30 board"
+
 config TARGET_BEAVER
        bool "NVIDIA Tegra30 Beaver evaluation board"
 
@@ -20,6 +23,7 @@ endchoice
 config SYS_SOC
        default "tegra30"
 
+source "board/toradex/apalis_t30/Kconfig"
 source "board/nvidia/beaver/Kconfig"
 source "board/nvidia/cardhu/Kconfig"
 source "board/toradex/colibri_t30/Kconfig"
index b385e19..781b511 100644 (file)
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
                sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
new file mode 100644 (file)
index 0000000..0047223
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK                36864000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
index 712afd1..e11f4f6 100644 (file)
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
                                sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
new file mode 100644 (file)
index 0000000..6da921e
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK                73728000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
index b385e19..781b511 100644 (file)
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
                sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
new file mode 100644 (file)
index 0000000..59d054a
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK                80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
index 433da09..b6a84a5 100644 (file)
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
+#include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
@@ -27,55 +28,6 @@ enum {
        UART_COUNT = 5,
 };
 
-#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
-       defined(CONFIG_TEGRA114)
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-unsigned int query_sdram_size(void)
-{
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-       u32 reg;
-
-       reg = readl(&pmc->pmc_scratch20);
-       debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
-
-#if defined(CONFIG_TEGRA20)
-       /* bits 30:28 in OdmData are used for RAM size on T20  */
-       reg &= 0x70000000;
-
-       switch ((reg) >> 28) {
-       case 1:
-               return 0x10000000;      /* 256 MB */
-       case 0:
-       case 2:
-       default:
-               return 0x20000000;      /* 512 MB */
-       case 3:
-               return 0x40000000;      /* 1GB */
-       }
-#else  /* Tegra30/Tegra114 */
-       /* bits 31:28 in OdmData are used for RAM size on T30  */
-       switch ((reg) >> 28) {
-       case 0:
-       case 1:
-       default:
-               return 0x10000000;      /* 256 MB */
-       case 2:
-               return 0x20000000;      /* 512 MB */
-       case 3:
-               return 0x30000000;      /* 768 MB */
-       case 4:
-               return 0x40000000;      /* 1GB */
-       case 8:
-               return 0x7ff00000;      /* 2GB - 1MB */
-       }
-#endif
-}
-#else
-#include <asm/arch/mc.h>
-
 /* Read the RAM size directly from the memory controller */
 unsigned int query_sdram_size(void)
 {
@@ -83,12 +35,22 @@ unsigned int query_sdram_size(void)
        u32 size_mb;
 
        size_mb = readl(&mc->mc_emem_cfg);
+#if defined(CONFIG_TEGRA20)
+       debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
+       size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+#else
        debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
+       size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+#endif
 
-       return size_mb * 1024 * 1024;
-}
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+       /* External memory limited to 2047 MB due to IROM/HI-VEC */
+       if (size_mb == SZ_2G) size_mb -= SZ_1M;
 #endif
 
+       return size_mb;
+}
+
 int dram_init(void)
 {
        /* We do not initialise DRAM here. We just query the size */
index de20325..5933c35 100644 (file)
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 
-void upstring(char *s)
+static void upstring(char *s)
 {
        while (*s) {
                *s = toupper(*s);
index c37580e..c346063 100644 (file)
@@ -22,6 +22,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
        tegra20-ventana.dtb \
        tegra20-whistler.dtb \
        tegra20-colibri_t20_iris.dtb \
+       tegra30-apalis.dtb \
        tegra30-beaver.dtb \
        tegra30-cardhu.dtb \
        tegra30-colibri.dtb \
index 2f66ded..e70b4d1 100644 (file)
        model = "TI AM335x BeagleBone";
        compatible = "ti,am335x-bone", "ti,am33xx";
 
+       chosen {
+               stdout-path = &uart0;
+       };
+
        cpus {
                cpu@0 {
                        cpu0-supply = <&dcdc2_reg>;
diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h
deleted file mode 100644 (file)
index e6b1e0a..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-#endif
index 110eb43..77fad48 100644 (file)
@@ -7,9 +7,16 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
+       combiner: interrupt-controller@10440000 {
+               compatible = "samsung,exynos4210-combiner";
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               reg = <0x10440000 0x1000>;
+       };
+
        serial@13800000 {
                compatible = "samsung,exynos4210-uart";
                reg = <0x13800000 0x3c>;
index 15059d2..dd2476c 100644 (file)
@@ -8,8 +8,8 @@
  */
 
 /dts-v1/;
-/include/ "skeleton.dtsi"
-/include/ "exynos4.dtsi"
+#include "skeleton.dtsi"
+#include "exynos4210.dtsi"
 
 / {
        model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
new file mode 100644 (file)
index 0000000..ee071c1
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+       pinctrl_0: pinctrl@11400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos4210-pinctrl";
+       };
+
+       pinctrl_1: pinctrl@11000000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpy0: gpy0 {
+                       reg = <0xc00>;
+               };
+       };
+
+       pinctrl_2: pinctrl@03860000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+};
diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..bda17f7
--- /dev/null
@@ -0,0 +1,304 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *             www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+       pinctrl@11400000 {
+               gpa0: gpa0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa1: gpa1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb: gpb {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc0: gpc0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc1: gpc1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd0: gpd0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd1: gpd1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe0: gpe0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe1: gpe1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe2: gpe2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe3: gpe3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe4: gpe4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf0: gpf0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf1: gpf1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf2: gpf2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf3: gpf3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@11000000 {
+               gpj0: gpj0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpj1: gpj1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk0: gpk0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk1: gpk1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk2: gpk2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk3: gpk3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl0: gpl0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl1: gpl1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl2: gpl2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpy0: gpy0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy1: gpy1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy2: gpy2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy3: gpy3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy4: gpy4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy5: gpy5 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy6: gpy6 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpx0: gpx0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                    <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx1: gpx1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                    <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx2: gpx2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx3: gpx3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@03860000 {
+               gpz: gpz {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+       };
+};
index c390c8f..00cad04 100644 (file)
@@ -7,7 +7,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4.dtsi"
 
 / {
        model = "Samsung SMDKV310 on Exynos4210";
index 0ff6939..81188bc 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4210.dtsi"
 
 / {
        model = "Samsung Trats based on Exynos4210";
index 6941906..9139810 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4210.dtsi"
 
 / {
        model = "Samsung Universal C210 based on Exynos4210 rev0";
                status = "disabled";
        };
 
+       soft-spi {
+               compatible = "u-boot,soft-spi";
+               cs-gpio = <&gpio 235 0>;        /* Y43 */
+               sclk-gpio = <&gpio 225 0>;      /* Y31 */
+               mosi-gpio = <&gpio 227 0>;      /* Y33 */
+               miso-gpio = <&gpio 224 0>;      /* Y30 */
+               spi-delay-us = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cs@0 {
+               };
+       };
+
        fimd@11c00000 {
                compatible = "samsung,exynos-fimd";
                reg = <0x11c00000 0xa4>;
diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi
new file mode 100644 (file)
index 0000000..634a5c1
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *             www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
+#include "exynos4210-pinctrl-uboot.dtsi"
+
+/ {
+       compatible = "samsung,exynos4210";
+
+       aliases {
+               pinctrl0 = &pinctrl_0;
+               pinctrl1 = &pinctrl_1;
+               pinctrl2 = &pinctrl_2;
+       };
+
+       pd_lcd1: lcd1-power-domain@10023CA0 {
+               compatible = "samsung,exynos4210-pd";
+               reg = <0x10023CA0 0x20>;
+       };
+
+       gic: interrupt-controller@10490000 {
+               cpu-offset = <0x8000>;
+       };
+
+       combiner: interrupt-controller@10440000 {
+               samsung,combiner-nr = <16>;
+               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+       };
+
+       mct@10050000 {
+               compatible = "samsung,exynos4210-mct";
+               reg = <0x10050000 0x800>;
+               interrupt-parent = <&mct_map>;
+               interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
+               clocks = <&clock 3>, <&clock 344>;
+               clock-names = "fin_pll", "mct";
+
+               mct_map: mct-map {
+                       #interrupt-cells = <1>;
+                       #address-cells = <0>;
+                       #size-cells = <0>;
+                       interrupt-map = <0 &gic 0 57 0>,
+                                       <1 &gic 0 69 0>,
+                                       <2 &combiner 12 6>,
+                                       <3 &combiner 12 7>,
+                                       <4 &gic 0 42 0>,
+                                       <5 &gic 0 48 0>;
+               };
+       };
+
+       clock: clock-controller@10030000 {
+               compatible = "samsung,exynos4210-clock";
+               reg = <0x10030000 0x20000>;
+               #clock-cells = <1>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupt-parent = <&combiner>;
+               interrupts = <2 2>, <3 2>;
+       };
+
+       pinctrl_0: pinctrl@11400000 {
+               compatible = "samsung,exynos4210-pinctrl";
+               reg = <0x11400000 0x1000>;
+               interrupts = <0 47 0>;
+       };
+
+       pinctrl_1: pinctrl@11000000 {
+               compatible = "samsung,exynos4210-pinctrl";
+               reg = <0x11000000 0x1000>;
+               interrupts = <0 46 0>;
+
+               wakup_eint: wakeup-interrupt-controller {
+                       compatible = "samsung,exynos4210-wakeup-eint";
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 32 0>;
+               };
+       };
+
+       pinctrl_2: pinctrl@03860000 {
+               compatible = "samsung,exynos4210-pinctrl";
+               reg = <0x03860000 0x1000>;
+       };
+
+       tmu@100C0000 {
+               compatible = "samsung,exynos4210-tmu";
+               interrupt-parent = <&combiner>;
+               reg = <0x100C0000 0x100>;
+               interrupts = <2 4>;
+               clocks = <&clock 383>;
+               clock-names = "tmu_apbif";
+               status = "disabled";
+       };
+
+       g2d@12800000 {
+               compatible = "samsung,s5pv210-g2d";
+               reg = <0x12800000 0x1000>;
+               interrupts = <0 89 0>;
+               clocks = <&clock 177>, <&clock 277>;
+               clock-names = "sclk_fimg2d", "fimg2d";
+               status = "disabled";
+       };
+
+       camera {
+               clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
+               clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+
+               fimc_0: fimc@11800000 {
+                       samsung,pix-limits = <4224 8192 1920 4224>;
+                       samsung,mainscaler-ext;
+                       samsung,cam-if;
+               };
+
+               fimc_1: fimc@11810000 {
+                       samsung,pix-limits = <4224 8192 1920 4224>;
+                       samsung,mainscaler-ext;
+                       samsung,cam-if;
+               };
+
+               fimc_2: fimc@11820000 {
+                       samsung,pix-limits = <4224 8192 1920 4224>;
+                       samsung,mainscaler-ext;
+                       samsung,lcd-wb;
+               };
+
+               fimc_3: fimc@11830000 {
+                       samsung,pix-limits = <1920 8192 1366 1920>;
+                       samsung,rotators = <0>;
+                       samsung,mainscaler-ext;
+                       samsung,lcd-wb;
+               };
+       };
+};
index 24d0bf1..4c5e2b3 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4.dtsi"
 
 / {
        model = "Odroid based on Exynos4412";
index cc58c87..3b1e458 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4412.dtsi"
 
 / {
        model = "Samsung Trats2 based on Exynos4412";
diff --git a/arch/arm/dts/exynos4412.dtsi b/arch/arm/dts/exynos4412.dtsi
new file mode 100644 (file)
index 0000000..87b339c
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * Samsung's Exynos4412 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos4x12.dtsi"
+
+/ {
+       compatible = "samsung,exynos4412";
+
+       gic: interrupt-controller@10490000 {
+               cpu-offset = <0x4000>;
+       };
+
+       interrupt-controller@10440000 {
+               samsung,combiner-nr = <20>;
+               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                            <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+       };
+
+};
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
new file mode 100644 (file)
index 0000000..c02796d
--- /dev/null
@@ -0,0 +1,46 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+       pinctrl_0: pinctrl@11400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpf0: gpf0 {
+                       reg = <0xc180>;
+               };
+               gpj0: gpj0 {
+                       reg = <0x240>;
+               };
+       };
+
+       pinctrl_1: pinctrl@11000000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpk0: gpk0 {
+                       reg = <0x40>;
+               };
+               gpm0: gpm0 {
+                       reg = <0x260>;
+               };
+               gpy0: gpy0 {
+                       reg = <0x120>;
+               };
+               gpx0: gpx0 {
+                       reg = <0xc00>;
+               };
+       };
+
+       pinctrl_2: pinctrl@03860000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       pinctrl_3: pinctrl@106E0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+};
diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..93f3998
--- /dev/null
@@ -0,0 +1,344 @@
+/*
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+       pinctrl@11400000 {
+               gpa0: gpa0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa1: gpa1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb: gpb {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc0: gpc0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc1: gpc1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd0: gpd0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd1: gpd1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf0: gpf0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf1: gpf1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf2: gpf2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf3: gpf3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpj0: gpj0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpj1: gpj1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       pinctrl@11000000 {
+               gpk0: gpk0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk1: gpk1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk2: gpk2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpk3: gpk3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl0: gpl0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl1: gpl1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpl2: gpl2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpm0: gpm0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpm1: gpm1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpm2: gpm2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpm3: gpm3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpm4: gpm4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpy0: gpy0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy1: gpy1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy2: gpy2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy3: gpy3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy4: gpy4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy5: gpy5 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy6: gpy6 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpx0: gpx0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                    <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx1: gpx1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                    <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx2: gpx2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx3: gpx3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       pinctrl@03860000 {
+               gpz: gpz {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       pinctrl@106E0000 {
+               gpv0: gpv0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv1: gpv1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv2: gpv2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv3: gpv3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv4: gpv4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+};
diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi
new file mode 100644 (file)
index 0000000..5d58c6e
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Samsung's Exynos4x12 SoCs device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+` * published by the Free Software Foundation.
+*/
+
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
+#include "exynos4x12-pinctrl-uboot.dtsi"
+
+/ {
+       aliases {
+               pinctrl0 = &pinctrl_0;
+               pinctrl1 = &pinctrl_1;
+               pinctrl2 = &pinctrl_2;
+               pinctrl3 = &pinctrl_3;
+               mshc0 = &mshc_0;
+       };
+
+       pd_isp: isp-power-domain@10023CA0 {
+               compatible = "samsung,exynos4210-pd";
+               reg = <0x10023CA0 0x20>;
+       };
+
+       clock: clock-controller@10030000 {
+               compatible = "samsung,exynos4412-clock";
+               reg = <0x10030000 0x20000>;
+               #clock-cells = <1>;
+       };
+
+       mct@10050000 {
+               compatible = "samsung,exynos4412-mct";
+               reg = <0x10050000 0x800>;
+               interrupt-parent = <&mct_map>;
+               interrupts = <0>, <1>, <2>, <3>, <4>;
+               clocks = <&clock 3>, <&clock 344>;
+               clock-names = "fin_pll", "mct";
+
+               mct_map: mct-map {
+                       #interrupt-cells = <1>;
+                       #address-cells = <0>;
+                       #size-cells = <0>;
+                       interrupt-map = <0 &gic 0 57 0>,
+                                       <1 &combiner 12 5>,
+                                       <2 &combiner 12 6>,
+                                       <3 &combiner 12 7>,
+                                       <4 &gic 1 12 0>;
+               };
+       };
+
+       pinctrl_0: pinctrl@11400000 {
+               compatible = "samsung,exynos4x12-pinctrl";
+               reg = <0x11400000 0x1000>;
+               interrupts = <0 47 0>;
+       };
+
+       pinctrl_1: pinctrl@11000000 {
+               compatible = "samsung,exynos4x12-pinctrl";
+               reg = <0x11000000 0x1000>;
+               interrupts = <0 46 0>;
+
+               wakup_eint: wakeup-interrupt-controller {
+                       compatible = "samsung,exynos4210-wakeup-eint";
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 32 0>;
+               };
+       };
+
+       pinctrl_2: pinctrl@03860000 {
+               compatible = "samsung,exynos4x12-pinctrl";
+               reg = <0x03860000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <10 0>;
+       };
+
+       pinctrl_3: pinctrl@106E0000 {
+               compatible = "samsung,exynos4x12-pinctrl";
+               reg = <0x106E0000 0x1000>;
+               interrupts = <0 72 0>;
+       };
+
+       g2d@10800000 {
+               compatible = "samsung,exynos4212-g2d";
+               reg = <0x10800000 0x1000>;
+               interrupts = <0 89 0>;
+               clocks = <&clock 177>, <&clock 277>;
+               clock-names = "sclk_fimg2d", "fimg2d";
+               status = "disabled";
+       };
+
+       mshc_0: mmc@12550000 {
+               compatible = "samsung,exynos4412-dw-mshc";
+               reg = <0x12550000 0x1000>;
+               interrupts = <0 77 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               fifo-depth = <0x80>;
+               clocks = <&clock 301>, <&clock 149>;
+               clock-names = "biu", "ciu";
+               status = "disabled";
+       };
+};
index a2b533a..e539068 100644 (file)
@@ -5,11 +5,38 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
        compatible = "samsung,exynos5";
 
+       combiner: interrupt-controller@10440000 {
+               compatible = "samsung,exynos4210-combiner";
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               samsung,combiner-nr = <32>;
+               reg = <0x10440000 0x1000>;
+               interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                               <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                               <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                               <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                               <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                               <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                               <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                               <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+       };
+
+       gic: interrupt-controller@10481000 {
+               compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg =   <0x10481000 0x1000>,
+                       <0x10482000 0x1000>,
+                       <0x10484000 0x2000>,
+                       <0x10486000 0x2000>;
+               interrupts = <1 9 0xf04>;
+       };
+
        sromc@12250000 {
                compatible = "samsung,exynos-sromc";
                reg = <0x12250000 0x20>;
                #size-cells = <0>;
        };
 
+       combiner: interrupt-controller@10440000 {
+               compatible = "samsung,exynos4210-combiner";
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               samsung,combiner-nr = <32>;
+               reg = <0x10440000 0x1000>;
+               interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                               <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                               <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                               <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                               <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                               <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                               <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                               <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+       };
+
+       gic: interrupt-controller@10481000 {
+               compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg =   <0x10481000 0x1000>,
+                       <0x10482000 0x1000>,
+                       <0x10484000 0x2000>,
+                       <0x10486000 0x2000>;
+               interrupts = <1 9 0xf04>;
+       };
+
        i2c@12c60000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,exynos4210-uart";
                reg = <0x12C30000 0x100>;
                interrupts = <0 54 0>;
+               u-boot,dm-pre-reloc;
                id = <3>;
        };
 
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
new file mode 100644 (file)
index 0000000..7edb0ca
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+       pinctrl_0: pinctrl@11400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpc4: gpc4 {
+                       reg = <0x2e0>;
+               };
+               gpx0: gpx0 {
+                       reg = <0xc00>;
+               };
+       };
+
+       pinctrl_1: pinctrl@13400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       pinctrl_2: pinctrl@10d10000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpv2: gpv2 {
+                       reg = <0x060>;
+               };
+               gpv4: gpv4 {
+                       reg = <0xc0>;
+               };
+       };
+
+       pinctrl_3: pinctrl@03860000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+};
diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..67755a1
--- /dev/null
@@ -0,0 +1,331 @@
+/*
+ * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+       pinctrl@11400000 {
+               gpa0: gpa0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa1: gpa1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa2: gpa2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb0: gpb0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb1: gpb1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb2: gpb2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb3: gpb3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc0: gpc0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc1: gpc1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc2: gpc2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc3: gpc3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd0: gpd0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd1: gpd1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpy0: gpy0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy1: gpy1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy2: gpy2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy3: gpy3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy4: gpy4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy5: gpy5 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy6: gpy6 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpc4: gpc4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx0: gpx0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&combiner>;
+                       #interrupt-cells = <2>;
+                       interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+                                    <26 0>, <26 1>, <27 0>, <27 1>;
+               };
+
+               gpx1: gpx1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&combiner>;
+                       #interrupt-cells = <2>;
+                       interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+                                    <30 0>, <30 1>, <31 0>, <31 1>;
+               };
+
+               gpx2: gpx2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx3: gpx3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       pinctrl@13400000 {
+               gpe0: gpe0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe1: gpe1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf0: gpf0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf1: gpf1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg0: gpg0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg1: gpg1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg2: gpg2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gph0: gph0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gph1: gph1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@10d10000 {
+               gpv0: gpv0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv1: gpv1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv2: gpv2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv3: gpv3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpv4: gpv4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@03860000 {
+               gpz: gpz {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+};
index 9020382..8850409 100644 (file)
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
index ab4f2f8..6fd9275 100644 (file)
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
        model = "Google Snow";
                };
        };
 
+       spi@12d30000 {
+               spi-max-frequency = <50000000>;
+               firmware_storage_spi: flash@0 {
+                       compatible = "spi-flash";
+                       reg = <0>;
+               };
+       };
+
        spi@131b0000 {
                spi-max-frequency = <1000000>;
                spi-deactivate-delay = <100>;
index 0c644e7..ccbafe9 100644 (file)
@@ -5,9 +5,48 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-/include/ "exynos5.dtsi"
+#include "exynos5.dtsi"
+#include "exynos5250-pinctrl.dtsi"
+#include "exynos5250-pinctrl-uboot.dtsi"
 
 / {
+       aliases {
+               pinctrl0 = &pinctrl_0;
+               pinctrl1 = &pinctrl_1;
+               pinctrl2 = &pinctrl_2;
+               pinctrl3 = &pinctrl_3;
+       };
+
+       pinctrl_0: pinctrl@11400000 {
+               compatible = "samsung,exynos5250-pinctrl";
+               reg = <0x11400000 0x1000>;
+               interrupts = <0 46 0>;
+
+               wakup_eint: wakeup-interrupt-controller {
+                       compatible = "samsung,exynos4210-wakeup-eint";
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 32 0>;
+               };
+       };
+
+       pinctrl_1: pinctrl@13400000 {
+               compatible = "samsung,exynos5250-pinctrl";
+               reg = <0x13400000 0x1000>;
+               interrupts = <0 45 0>;
+       };
+
+       pinctrl_2: pinctrl@10d10000 {
+               compatible = "samsung,exynos5250-pinctrl";
+               reg = <0x10d10000 0x1000>;
+               interrupts = <0 50 0>;
+       };
+
+       pinctrl_3: pinctrl@03860000 {
+               compatible = "samsung,exynos5250-pinctrl";
+               reg = <0x03860000 0x1000>;
+               interrupts = <0 47 0>;
+       };
+
        i2c@12ca0000 {
                #address-cells = <1>;
                #size-cells = <0>;
index 995e62b..fde863d 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos54xx.dtsi"
+#include "exynos54xx.dtsi"
 
 / {
        model = "Samsung/Google Peach Pit board based on Exynos5420";
        spi@12d30000 { /* spi1 */
                spi-max-frequency = <50000000>;
                firmware_storage_spi: flash@0 {
+                       compatible = "spi-flash";
                        reg = <0>;
 
                        /*
index 1bc6256..6855027 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos54xx.dtsi"
+#include "exynos54xx.dtsi"
 
 / {
        model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
new file mode 100644 (file)
index 0000000..5a86211
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+       /*
+        * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h
+        * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO
+        * numbers are not needed in U-Boot for exynos.
+        */
+       pinctrl@14010000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+       pinctrl@13400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpy7 {
+               };
+
+               gpx0 {
+                       reg = <0xc00>;
+               };
+       };
+       pinctrl@13410000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+       pinctrl@14000000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+       pinctrl@03860000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+};
diff --git a/arch/arm/dts/exynos54xx-pinctrl.dtsi b/arch/arm/dts/exynos54xx-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..775d956
--- /dev/null
@@ -0,0 +1,305 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos54xx-pinctrl-uboot.dtsi"
+
+/ {
+       pinctrl@13400000 {
+               gpy7: gpy7 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx0: gpx0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&combiner>;
+                       #interrupt-cells = <2>;
+                       interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+                                    <26 0>, <26 1>, <27 0>, <27 1>;
+               };
+
+               gpx1: gpx1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       interrupt-parent = <&combiner>;
+                       #interrupt-cells = <2>;
+                       interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+                                    <30 0>, <30 1>, <31 0>, <31 1>;
+               };
+
+               gpx2: gpx2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpx3: gpx3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@13410000 {
+               gpc0: gpc0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc1: gpc1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc2: gpc2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc3: gpc3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpc4: gpc4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpd1: gpd1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpy0: gpy0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy1: gpy1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy2: gpy2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy3: gpy3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy4: gpy4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy5: gpy5 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpy6: gpy6 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+       };
+
+       pinctrl@14000000 {
+               gpe0: gpe0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpe1: gpe1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf0: gpf0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpf1: gpf1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg0: gpg0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg1: gpg1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpg2: gpg2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpj4: gpj4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@14010000 {
+               gpa0: gpa0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa1: gpa1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpa2: gpa2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb0: gpb0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb1: gpb1 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb2: gpb2 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb3: gpb3 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpb4: gpb4 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gph0: gph0 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+
+       pinctrl@03860000 {
+               gpz: gpz {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+       };
+};
index c21d798..916cf3a 100644 (file)
@@ -5,7 +5,8 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-/include/ "exynos5.dtsi"
+#include "exynos5.dtsi"
+#include "exynos54xx-pinctrl.dtsi"
 
 / {
        config {
                i2c8 = "/i2c@12e00000";
                i2c9 = "/i2c@12e10000";
                i2c10 = "/i2c@12e20000";
+               pinctrl0 = &pinctrl_0;
+               pinctrl1 = &pinctrl_1;
+               pinctrl2 = &pinctrl_2;
+               pinctrl3 = &pinctrl_3;
+               pinctrl4 = &pinctrl_4;
                spi0 = "/spi@12d20000";
                spi1 = "/spi@12d30000";
                spi2 = "/spi@12d40000";
                reg = <0x14680000 0x100>;
        };
 
+       pinctrl_0: pinctrl@13400000 {
+               compatible = "samsung,exynos5420-pinctrl";
+               reg = <0x13400000 0x1000>;
+               interrupts = <0 45 0>;
+
+               wakeup-interrupt-controller {
+                       compatible = "samsung,exynos4210-wakeup-eint";
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 32 0>;
+               };
+       };
+
+       pinctrl_1: pinctrl@13410000 {
+               compatible = "samsung,exynos5420-pinctrl";
+               reg = <0x13410000 0x1000>;
+               interrupts = <0 78 0>;
+       };
+
+       pinctrl_2: pinctrl@14000000 {
+               compatible = "samsung,exynos5420-pinctrl";
+               reg = <0x14000000 0x1000>;
+               interrupts = <0 46 0>;
+       };
+
+       pinctrl_3: pinctrl@14010000 {