Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
authorWolfgang Denk <wd@denx.de>
Wed, 7 Dec 2011 22:01:26 +0000 (23:01 +0100)
committerWolfgang Denk <wd@denx.de>
Wed, 7 Dec 2011 22:01:26 +0000 (23:01 +0100)
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/83xx: fix sdram initialization for keymile boards
  powerpc/mpc83xx: cleanup makefile for mpc83xx

816 files changed:
.checkpatch.conf [new file with mode: 0644]
.gitignore
CREDITS
MAINTAINERS
MAKEALL
Makefile
README
api/Makefile
api/api.c
api/api_display.c [new file with mode: 0644]
api/api_private.h
arch/arm/cpu/arm1136/mx31/devices.c
arch/arm/cpu/arm1136/mx31/generic.c
arch/arm/cpu/arm920t/a320/timer.c
arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
arch/arm/cpu/arm926ejs/Makefile
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
arch/arm/cpu/arm926ejs/at91/led.c
arch/arm/cpu/arm926ejs/at91/reset.c
arch/arm/cpu/arm926ejs/at91/timer.c
arch/arm/cpu/arm926ejs/cache.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/davinci/Makefile
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
arch/arm/cpu/arm926ejs/davinci/dp83848.c
arch/arm/cpu/arm926ejs/davinci/et1011c.c
arch/arm/cpu/arm926ejs/davinci/ksz8873.c
arch/arm/cpu/arm926ejs/davinci/lxt972.c
arch/arm/cpu/arm926ejs/davinci/misc.c [moved from board/davinci/common/misc.c with 90% similarity]
arch/arm/cpu/arm926ejs/davinci/pinmux.c [moved from board/davinci/common/davinci_pinmux.c with 100% similarity]
arch/arm/cpu/arm926ejs/mb86r0x/timer.c
arch/arm/cpu/arm926ejs/mx28/Makefile [moved from board/pleb2/Makefile with 86% similarity]
arch/arm/cpu/arm926ejs/mx28/clock.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mx28/iomux.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mx28/mx28.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mx28/timer.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/omap/cpuinfo.c
arch/arm/cpu/arm926ejs/start.S
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/clocks-common.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/emif-common.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/hwinit-common.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/lowlevel_init.S [moved from arch/arm/cpu/armv7/omap4/lowlevel_init.S with 76% similarity]
arch/arm/cpu/armv7/omap-common/mem-common.c [moved from arch/arm/cpu/armv7/omap4/mem.c with 100% similarity]
arch/arm/cpu/armv7/omap-common/spl.c
arch/arm/cpu/armv7/omap3/Makefile
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/emac.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap3/lowlevel_init.S
arch/arm/cpu/armv7/omap3/mem.c
arch/arm/cpu/armv7/omap3/sdrc.c
arch/arm/cpu/armv7/omap3/spl_id_nand.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap4/Makefile
arch/arm/cpu/armv7/omap4/board.c [deleted file]
arch/arm/cpu/armv7/omap4/clocks.c
arch/arm/cpu/armv7/omap4/emif.c
arch/arm/cpu/armv7/omap4/hwinit.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap4/omap4_mux_data.h [deleted file]
arch/arm/cpu/armv7/omap4/sdram_elpida.c
arch/arm/cpu/armv7/omap5/Makefile [moved from board/cerf250/Makefile with 81% similarity]
arch/arm/cpu/armv7/omap5/clocks.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/config.mk [moved from board/ti/evm/config.mk with 66% similarity]
arch/arm/cpu/armv7/omap5/emif.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/hwinit.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/sdram_elpida.c [new file with mode: 0644]
arch/arm/cpu/armv7/s5p-common/pwm.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/pxa/Makefile
arch/arm/cpu/pxa/cpuinfo.c [new file with mode: 0644]
arch/arm/cpu/pxa/pxa2xx.c [moved from arch/arm/cpu/pxa/cpu.c with 76% similarity]
arch/arm/cpu/pxa/start.S
arch/arm/cpu/pxa/timer.c
arch/arm/cpu/pxa/u-boot.lds
arch/arm/cpu/pxa/usb.c
arch/arm/include/asm/arch-at91/at91_common.h
arch/arm/include/asm/arch-at91/at91cap9.h
arch/arm/include/asm/arch-at91/at91cap9_matrix.h
arch/arm/include/asm/arch-at91/clk.h
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-davinci/aintc_defs.h
arch/arm/include/asm/arch-davinci/da850_lowlevel.h [moved from arch/arm/include/asm/arch-davinci/am1808_lowlevel.h with 63% similarity]
arch/arm/include/asm/arch-davinci/davinci_misc.h
arch/arm/include/asm/arch-davinci/ddr2_defs.h
arch/arm/include/asm/arch-davinci/emac_defs.h
arch/arm/include/asm/arch-davinci/emif_defs.h
arch/arm/include/asm/arch-davinci/hardware.h
arch/arm/include/asm/arch-davinci/pinmux_defs.h [new file with mode: 0644]
arch/arm/include/asm/arch-davinci/pll_defs.h
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx27/imx-regs.h
arch/arm/include/asm/arch-mx28/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/dma.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/imx-regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/iomux-mx28.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/iomux.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-apbh.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-base.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-bch.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-clkctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-common.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-gpmi.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-i2c.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-ocotp.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-pinctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-power.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-rtc.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-ssp.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-timrot.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-usb.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-usbphy.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/sys_proto.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-omap3/am35x_def.h
arch/arm/include/asm/arch-omap3/emac_defs.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap3/mem.h
arch/arm/include/asm/arch-omap3/mmc_host_def.h
arch/arm/include/asm/arch-omap3/mux.h
arch/arm/include/asm/arch-omap3/omap3.h
arch/arm/include/asm/arch-omap3/sys_proto.h
arch/arm/include/asm/arch-omap4/clocks.h
arch/arm/include/asm/arch-omap4/emif.h [deleted file]
arch/arm/include/asm/arch-omap4/mmc_host_def.h
arch/arm/include/asm/arch-omap4/omap.h [moved from arch/arm/include/asm/arch-omap4/omap4.h with 87% similarity]
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clocks.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/cpu.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/i2c.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/mmc_host_def.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/mux_omap5.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/omap.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/sys_proto.h [new file with mode: 0644]
arch/arm/include/asm/arch-pxa/pxa-regs.h
arch/arm/include/asm/arch-pxa/pxa.h [moved from arch/arm/cpu/armv7/omap4/sys_info.c with 60% similarity]
arch/arm/include/asm/arch-pxa/regs-uart.h [new file with mode: 0644]
arch/arm/include/asm/armv7.h
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/emif.h [new file with mode: 0644]
arch/arm/include/asm/mach-types.h
arch/arm/include/asm/omap_common.h
arch/arm/lib/board.c
arch/arm/lib/eabi_compat.c
arch/blackfin/config.mk
arch/blackfin/cpu/traps.c
arch/blackfin/lib/board.c
arch/m68k/cpu/mcf52x2/cpu_init.c
arch/nds32/cpu/n1213/ag101/cpu.c
arch/nds32/cpu/n1213/ag101/timer.c
arch/nds32/cpu/n1213/u-boot.lds
arch/nds32/include/asm/io.h
arch/nds32/include/asm/mach-types.h
arch/nds32/lib/board.c
arch/nios2/cpu/Makefile
arch/nios2/cpu/cpu.c
arch/nios2/cpu/fdt.c [new file with mode: 0644]
arch/nios2/include/asm/gpio.h
arch/powerpc/cpu/mpc512x/i2c.c
arch/powerpc/cpu/mpc512x/pci.c
arch/powerpc/cpu/mpc83xx/spd_sdram.c
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/tlb.c
arch/powerpc/cpu/mpc86xx/cpu.c
arch/powerpc/cpu/mpc8xx/video.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
arch/powerpc/cpu/ppc4xx/4xx_pcie.c
arch/powerpc/cpu/ppc4xx/Makefile
arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
arch/powerpc/cpu/ppc4xx/iop480_uart.c
arch/powerpc/cpu/ppc4xx/usb.c
arch/powerpc/cpu/ppc4xx/usb_ohci.c
arch/powerpc/cpu/ppc4xx/usbdev.c [deleted file]
arch/powerpc/cpu/ppc4xx/usbdev.h [deleted file]
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/processor.h
arch/sh/cpu/sh2/config.mk
arch/sh/cpu/sh4/cache.c
arch/sh/include/asm/cache.h
arch/sh/include/asm/cpu_sh4.h
arch/sh/include/asm/cpu_sh7724.h [new file with mode: 0644]
arch/sh/lib/Makefile
arch/sh/lib/ashrsi3.S [new file with mode: 0644]
arch/sparc/lib/board.c
arch/sparc/lib/bootm.c
arch/x86/config.mk
arch/x86/cpu/cpu.c
arch/x86/cpu/interrupts.c
arch/x86/cpu/sc520/asm-offsets.c [new file with mode: 0644]
arch/x86/cpu/sc520/sc520.c
arch/x86/cpu/sc520/sc520_car.S
arch/x86/cpu/sc520/sc520_pci.c
arch/x86/cpu/sc520/sc520_sdram.c
arch/x86/cpu/sc520/sc520_ssi.c
arch/x86/cpu/sc520/sc520_timer.c
arch/x86/cpu/start.S
arch/x86/cpu/start16.S
arch/x86/include/asm/arch-sc520/sc520.h
arch/x86/include/asm/global_data.h
arch/x86/include/asm/pci.h
arch/x86/include/asm/realmode.h
arch/x86/include/asm/string.h
arch/x86/include/asm/u-boot-x86.h
arch/x86/lib/Makefile
arch/x86/lib/bios.h
arch/x86/lib/bios_pci.S
arch/x86/lib/bios_setup.c
arch/x86/lib/board.c
arch/x86/lib/bootm.c
arch/x86/lib/gcc.c [new file with mode: 0644]
arch/x86/lib/interrupts.c
arch/x86/lib/pcat_interrupts.c
arch/x86/lib/pcat_timer.c
arch/x86/lib/pci.c
arch/x86/lib/pci_type1.c
arch/x86/lib/realmode.c
arch/x86/lib/string.c [new file with mode: 0644]
arch/x86/lib/timer.c
arch/x86/lib/video.c
arch/x86/lib/video_bios.c
arch/x86/lib/zimage.c
board/AndesTech/adp-ag101p/Makefile [new file with mode: 0644]
board/AndesTech/adp-ag101p/adp-ag101p.c [new file with mode: 0644]
board/CarMediaLab/flea3/flea3.c
board/LaCie/common/common.c [new file with mode: 0644]
board/LaCie/common/common.h [new file with mode: 0644]
board/LaCie/edminiv2/Makefile
board/LaCie/edminiv2/edminiv2.c
board/LaCie/net2big_v2/Makefile [new file with mode: 0644]
board/LaCie/net2big_v2/kwbimage.cfg [new file with mode: 0644]
board/LaCie/net2big_v2/net2big_v2.c [new file with mode: 0644]
board/LaCie/net2big_v2/net2big_v2.h [moved from board/LaCie/edminiv2/edminiv2.h with 50% similarity]
board/LaCie/netspace_v2/Makefile
board/LaCie/netspace_v2/netspace_v2.c
board/LaCie/netspace_v2/netspace_v2.h
board/Marvell/db64360/db64360.c
board/Marvell/db64360/mv_eth.c
board/Marvell/db64360/sdram_init.c
board/Marvell/db64460/db64460.c
board/Marvell/db64460/mv_eth.c
board/Marvell/db64460/sdram_init.c
board/afeb9260/Makefile
board/afeb9260/afeb9260.c
board/ait/cam_enc_4xx/cam_enc_4xx.c
board/altera/nios2-generic/Makefile
board/altera/nios2-generic/custom_fpga.h
board/altera/nios2-generic/gpio.c [deleted file]
board/altera/nios2-generic/nios2-generic.c
board/amcc/common/flash.c
board/amcc/taihu/flash.c
board/amcc/yucca/cmd_yucca.c
board/amcc/yucca/flash.c
board/amirix/ap1000/flash.c
board/armltd/integrator/arm-ebi.h [new file with mode: 0644]
board/armltd/integrator/config.mk [deleted file]
board/armltd/integrator/integrator-sc.h [new file with mode: 0644]
board/armltd/integrator/integrator.c
board/atmel/at91sam9260ek/Makefile
board/atmel/at91sam9260ek/at91sam9260ek.c
board/atmel/at91sam9260ek/led.c
board/atmel/at91sam9261ek/Makefile
board/atmel/at91sam9261ek/at91sam9261ek.c
board/atmel/at91sam9261ek/led.c
board/atmel/at91sam9263ek/Makefile
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9263ek/led.c
board/atmel/at91sam9m10g45ek/Makefile
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9m10g45ek/led.c
board/atmel/at91sam9rlek/Makefile
board/atmel/at91sam9rlek/at91sam9rlek.c
board/atmel/at91sam9rlek/led.c
board/balloon3/balloon3.c
board/calao/sbc35_a9g20/Makefile
board/calao/sbc35_a9g20/sbc35_a9g20.c
board/calao/tny_a9260/Makefile
board/calao/tny_a9260/tny_a9260.c
board/cerf250/cerf250.c [deleted file]
board/cerf250/flash.c [deleted file]
board/cm4008/flash.c
board/cm41xx/flash.c
board/cradle/cradle.c [deleted file]
board/cradle/flash.c [deleted file]
board/cray/L1/flash.c
board/csb226/csb226.c [deleted file]
board/csb226/flash.c [deleted file]
board/davedenx/qong/qong.c
board/davinci/da8xxevm/da830evm.c
board/davinci/da8xxevm/da850evm.c
board/davinci/da8xxevm/hawkboard.c
board/davinci/da8xxevm/hawkboard_nand_spl.c
board/davinci/dm6467evm/dm6467evm.c
board/davinci/ea20/ea20.c
board/davinci/schmoogie/schmoogie.c
board/davinci/sonata/sonata.c
board/denx/m28evk/Makefile [moved from board/cradle/Makefile with 85% similarity]
board/denx/m28evk/m28_init.h [moved from onenand_ipl/board/vpac270/vpac270.c with 64% similarity]
board/denx/m28evk/m28evk.c [new file with mode: 0644]
board/denx/m28evk/mem_init.c [new file with mode: 0644]
board/denx/m28evk/mmc_boot.c [new file with mode: 0644]
board/denx/m28evk/power_init.c [new file with mode: 0644]
board/denx/m28evk/start.S [new file with mode: 0644]
board/denx/m28evk/u-boot-spl.lds [new file with mode: 0644]
board/denx/m28evk/u-boot.bd [new file with mode: 0644]
board/eNET/eNET.c
board/eNET/eNET_pci.c
board/eNET/eNET_start16.S
board/efikamx/efikamx.c
board/egnite/ethernut5/Makefile [new file with mode: 0644]
board/egnite/ethernut5/ethernut5.c [new file with mode: 0644]
board/egnite/ethernut5/ethernut5_pwrman.c [new file with mode: 0644]
board/egnite/ethernut5/ethernut5_pwrman.h [new file with mode: 0644]
board/eltec/bab7xx/misc.c
board/eltec/elppc/misc.c
board/eltec/mhpc/mhpc.c
board/emk/top860/top860.c
board/emk/top9000/top9000.c
board/enbw/enbw_cmc/Makefile [moved from board/davinci/common/Makefile with 88% similarity]
board/enbw/enbw_cmc/enbw_cmc.c [new file with mode: 0644]
board/esd/common/auto_update.c
board/esd/common/xilinx_jtag/micro.c
board/esd/cpci405/cpci405.c
board/esd/cpci750/cpci750.c
board/esd/cpci750/sdram_init.c
board/esd/dasa_sim/cmd_dasa_sim.c
board/esd/dasa_sim/flash.c
board/esd/meesc/Makefile
board/esd/meesc/meesc.c
board/esd/otc570/Makefile
board/esd/otc570/otc570.c
board/esd/pci405/cmd_pci405.c
board/esd/pmc440/cmd_pmc440.c
board/esd/pmc440/pmc440.c
board/eukrea/cpu9260/Makefile
board/eukrea/cpu9260/cpu9260.c
board/evb64260/eth.c
board/evb64260/evb64260.c
board/evb64260/i2c.c
board/evb64260/sdram_init.c
board/evb64260/zuma_pbb_mbox.c
board/faraday/a320evb/a320evb.c
board/freescale/common/Makefile
board/freescale/common/cds_pci_ft.c
board/freescale/common/ics307_clk.c
board/freescale/common/ics307_clk.h
board/freescale/common/ngpixis.c
board/freescale/common/pixis.c
board/freescale/common/qixis.c [new file with mode: 0644]
board/freescale/common/qixis.h [new file with mode: 0644]
board/freescale/corenet_ds/eth_hydra.c
board/freescale/corenet_ds/eth_p4080.c
board/freescale/mpc8360emds/mpc8360emds.c
board/freescale/mpc8548cds/mpc8548cds.c
board/freescale/mpc8568mds/mpc8568mds.c
board/freescale/mpc8569mds/mpc8569mds.c
board/freescale/mpc8572ds/tlb.c
board/freescale/mpc8610hpcd/mpc8610hpcd.c
board/freescale/mx51evk/mx51evk.c
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53smd/mx53smd.c
board/freescale/p1010rdb/p1010rdb.c
board/freescale/p1_p2_rdb/p1_p2_rdb.c
board/freescale/p1_p2_rdb_pc/law.c
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
board/freescale/p2020come/Makefile [new file with mode: 0644]
board/freescale/p2020come/ddr.c [moved from onenand_ipl/board/vpac270/u-boot.onenand.lds with 56% similarity]
board/freescale/p2020come/law.c [new file with mode: 0644]
board/freescale/p2020come/p2020come.c [new file with mode: 0644]
board/freescale/p2020come/tlb.c [new file with mode: 0644]
board/freescale/p2041rdb/eth.c
board/freescale/p2041rdb/p2041rdb.c
board/freescale/p3060qds/Makefile [new file with mode: 0644]
board/freescale/p3060qds/ddr.c [new file with mode: 0644]
board/freescale/p3060qds/eth.c [new file with mode: 0644]
board/freescale/p3060qds/fixed_ddr.c [new file with mode: 0644]
board/freescale/p3060qds/p3060qds.c [new file with mode: 0644]
board/freescale/p3060qds/p3060qds.h [new file with mode: 0644]
board/freescale/p3060qds/p3060qds_qixis.h [new file with mode: 0644]
board/gdsys/405ep/dlvision-10g.c
board/gdsys/405ex/405ex.c [new file with mode: 0644]
board/gdsys/405ex/405ex.h [new file with mode: 0644]
board/gdsys/405ex/Makefile [new file with mode: 0644]
board/gdsys/405ex/chip_config.c [new file with mode: 0644]
board/gdsys/405ex/io64.c [new file with mode: 0644]
board/gdsys/common/Makefile
board/gdsys/common/miiphybb.c
board/hymod/input.c
board/innokom/flash.c [deleted file]
board/innokom/innokom.c [deleted file]
board/keymile/km83xx/km83xx_i2c.c
board/logicpd/am3517evm/am3517evm.c
board/logicpd/am3517evm/am3517evm.h
board/logicpd/am3517evm/config.mk [deleted file]
board/lubbock/flash.c
board/lubbock/lubbock.c
board/matrix_vision/common/mv_common.c
board/matrix_vision/mvblx/Makefile
board/mcc200/lcd.c
board/mpl/common/flash.c
board/mpl/mip405/mip405.c
board/mpl/pip405/pip405.c
board/mpl/vcma9/vcma9.c
board/mx1ads/mx1ads.c
board/mx1ads/syncflash.c
board/palmld/palmld.c
board/palmtc/palmtc.c
board/pleb2/flash.c [deleted file]
board/pleb2/pleb2.c [deleted file]
board/prodrive/alpr/fpga.c
board/prodrive/alpr/nand.c
board/pxa255_idp/pxa_idp.c
board/renesas/ecovec/Makefile [moved from board/xm250/Makefile with 74% similarity]
board/renesas/ecovec/ecovec.c [new file with mode: 0644]
board/renesas/ecovec/lowlevel_init.S [new file with mode: 0644]
board/renesas/sh7757lcr/lowlevel_init.S
board/ronetix/pm9261/Makefile
board/ronetix/pm9261/led.c
board/ronetix/pm9261/pm9261.c
board/ronetix/pm9263/Makefile
board/ronetix/pm9263/led.c
board/ronetix/pm9263/pm9263.c
board/ronetix/pm9g45/Makefile
board/ronetix/pm9g45/pm9g45.c
board/sandburst/common/flash.c
board/sbc405/strataflash.c
board/sbc8548/sbc8548.c
board/sbc8560/sbc8560.c
board/syteco/jadecpu/Makefile
board/syteco/zmx25/zmx25.c
board/ti/am3517crane/am3517crane.c
board/ti/am3517crane/am3517crane.h
board/ti/am3517crane/config.mk [deleted file]
board/ti/beagle/beagle.c
board/ti/beagle/config.mk [deleted file]
board/ti/evm/evm.c
board/ti/omap5_evm/Makefile [moved from board/innokom/Makefile with 86% similarity]
board/ti/omap5_evm/evm.c [new file with mode: 0644]
board/ti/omap5_evm/mux_data.h [new file with mode: 0644]
board/ti/panda/Makefile
board/ti/panda/panda.c
board/ti/panda/panda_mux_data.h
board/ti/sdp4430/Makefile
board/ti/sdp4430/sdp.c
board/ti/sdp4430/sdp4430_mux_data.h
board/timll/devkit8000/devkit8000.c
board/toradex/colibri_pxa270/Makefile [moved from board/colibri_pxa270/Makefile with 100% similarity]
board/toradex/colibri_pxa270/colibri_pxa270.c [moved from board/colibri_pxa270/colibri_pxa270.c with 81% similarity]
board/trizepsiv/conxs.c
board/vpac270/Makefile
board/vpac270/onenand.c [new file with mode: 0644]
board/vpac270/u-boot-spl.lds [new file with mode: 0644]
board/vpac270/vpac270.c
board/xaeniax/flash.c
board/xaeniax/xaeniax.c
board/xm250/flash.c [deleted file]
board/xm250/xm250.c [deleted file]
board/zeus/zeus.c
board/zipitz2/zipitz2.c
boards.cfg
common/Makefile
common/cmd_bdinfo.c
common/cmd_bedbug.c
common/cmd_bmp.c
common/cmd_bootm.c
common/cmd_dcr.c
common/cmd_fdc.c
common/cmd_i2c.c
common/cmd_mem.c
common/cmd_nvedit.c
common/cmd_pci.c
common/cmd_pxe.c
common/cmd_tpm.c [new file with mode: 0644]
common/cmd_tsi148.c
common/cmd_universe.c
common/env_common.c
common/env_dataflash.c
common/env_eeprom.c
common/env_embedded.c
common/env_flash.c
common/env_mgdisk.c
common/env_mmc.c
common/env_nand.c
common/env_nowhere.c
common/env_nvram.c
common/env_onenand.c
common/env_sf.c
common/exports.c
common/fdt_support.c
common/hush.c
common/image.c
common/lcd.c
common/menu.c
common/miiphyutil.c
common/modem.c
common/serial.c
common/usb.c
disk/part_efi.c
doc/README.m28 [new file with mode: 0644]
doc/README.p3060qds [new file with mode: 0644]
doc/README.scrapyard
doc/README.sh7757lcr
doc/feature-removal-schedule.txt
doc/git-mailrc [new file with mode: 0644]
drivers/bios_emulator/x86emu/ops.c
drivers/bios_emulator/x86emu/ops2.c
drivers/block/ahci.c
drivers/block/fsl_sata.c
drivers/block/fsl_sata.h
drivers/block/ftide020.c
drivers/block/mvsata_ide.c
drivers/block/sata_dwc.c
drivers/block/sata_sil3114.c
drivers/block/sym53c8xx.c
drivers/dma/Makefile
drivers/dma/apbh_dma.c [new file with mode: 0644]
drivers/fpga/ivm_core.c
drivers/gpio/Makefile
drivers/gpio/altera_pio.c [new file with mode: 0644]
drivers/gpio/mxs_gpio.c [new file with mode: 0644]
drivers/gpio/pca9698.c
drivers/i2c/Makefile
drivers/i2c/davinci_i2c.c
drivers/i2c/fsl_i2c.c
drivers/i2c/mxs_i2c.c [new file with mode: 0644]
drivers/i2c/sh_i2c.c [new file with mode: 0644]
drivers/input/i8042.c
drivers/mmc/Makefile
drivers/mmc/arm_pl180_mmci.c
drivers/mmc/davinci_mmc.c
drivers/mmc/mmc.c
drivers/mmc/mv_sdhci.c
drivers/mmc/mxsmmc.c [new file with mode: 0644]
drivers/mmc/omap_hsmmc.c
drivers/mmc/pxa_mmc.c
drivers/mmc/pxa_mmc_gen.c
drivers/mmc/tegra2_mmc.c
drivers/mmc/tegra2_mmc.h
drivers/mtd/dataflash.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/mxs_nand.c [new file with mode: 0644]
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_ecc.c
drivers/mtd/nand/nand_spl_simple.c
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/nand/s3c64xx.c
drivers/mtd/onenand/Makefile
drivers/mtd/onenand/onenand_base.c
drivers/mtd/onenand/onenand_spl.c [new file with mode: 0644]
drivers/mtd/onenand/samsung.c
drivers/mtd/spi/spi_flash.c
drivers/net/4xx_enet.c
drivers/net/Makefile
drivers/net/armada100_fec.c
drivers/net/at91_emac.c
drivers/net/cs8900.c
drivers/net/davinci_emac.c
drivers/net/davinci_emac.h [new file with mode: 0644]
drivers/net/dnet.c
drivers/net/e1000.c
drivers/net/e1000.h
drivers/net/enc28j60.c
drivers/net/fec_mxc.c
drivers/net/fm/fm.c
drivers/net/lan91c96.c
drivers/net/lan91c96.h
drivers/net/mvgbe.c
drivers/net/phy/Makefile
drivers/net/phy/marvell.c
drivers/net/phy/phy.c
drivers/net/phy/smsc.c [new file with mode: 0644]
drivers/net/rtl8019.c [deleted file]
drivers/net/rtl8019.h [deleted file]
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/net/smc91111.h
drivers/net/smc911x.h
drivers/net/tsec.c
drivers/pci/Makefile
drivers/pci/pci_ftpci100.c [new file with mode: 0644]
drivers/pci/pci_ftpci100.h [new file with mode: 0644]
drivers/qe/qe.c
drivers/qe/uec.c
drivers/rtc/Makefile
drivers/rtc/davinci.c
drivers/rtc/mxsrtc.c [new file with mode: 0644]
drivers/rtc/s3c24x0_rtc.c
drivers/serial/serial_mxc.c
drivers/serial/serial_pxa.c
drivers/serial/usbtty.h
drivers/spi/Makefile
drivers/spi/atmel_spi.c
drivers/spi/mxs_spi.c [new file with mode: 0644]
drivers/tpm/Makefile [moved from board/csb226/Makefile with 84% similarity]
drivers/tpm/generic_lpc_tpm.c [new file with mode: 0644]
drivers/usb/eth/smsc95xx.c
drivers/usb/gadget/Makefile
drivers/usb/host/Makefile
drivers/usb/host/ehci-fsl.c
drivers/usb/host/ehci-mxs.c [new file with mode: 0644]
drivers/usb/host/sl811-hcd.c
drivers/usb/musb/musb_hcd.c
drivers/video/bus_vcxk.c
drivers/video/cfb_console.c
drivers/video/ct69000.c
drivers/video/da8xx-fb.c
drivers/video/fsl_diu_fb.c
drivers/video/mx3fb.c
drivers/video/sed156x.c
examples/api/demo.c
examples/api/glue.c
examples/api/glue.h
examples/standalone/atmel_df_pow2.c
examples/standalone/stubs.c
fs/yaffs2/yaffs_guts.c
fs/yaffs2/yaffs_tagscompat.c
include/.gitignore
include/andestech/andes_pcu.h [new file with mode: 0644]
include/api_public.h
include/command.h
include/common.h
include/compiler.h
include/config_phylib_all_drivers.h
include/configs/MPC8536DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8569MDS.h
include/configs/MPC8572DS.h
include/configs/P1022DS.h
include/configs/P1023RDS.h
include/configs/P1_P2_RDB.h
include/configs/P2020COME.h [new file with mode: 0644]
include/configs/P2041RDB.h
include/configs/P3041DS.h
include/configs/P3060QDS.h [new file with mode: 0644]
include/configs/P5020DS.h
include/configs/PMC440.h
include/configs/VCMA9.h
include/configs/a320evb.h
include/configs/adp-ag101p.h [new file with mode: 0644]
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/apollon.h
include/configs/at91sam9260ek.h
include/configs/at91sam9261ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9rlek.h
include/configs/balloon3.h
include/configs/cerf250.h [deleted file]
include/configs/cm_t35.h
include/configs/colibri_pxa270.h
include/configs/corenet_ds.h
include/configs/cpu9260.h
include/configs/cradle.h [deleted file]
include/configs/csb226.h [deleted file]
include/configs/da850_am18xxevm.h [new file with mode: 0644]
include/configs/da850evm.h
include/configs/davinci_dm6467Tevm.h [new file with mode: 0644]
include/configs/davinci_dm6467evm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sonata.h
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/eNET.h
include/configs/ecovec.h [new file with mode: 0644]
include/configs/efikamx.h
include/configs/enbw_cmc.h [new file with mode: 0644]
include/configs/espt.h
include/configs/ethernut5.h [new file with mode: 0644]
include/configs/flea3.h
include/configs/gr_cpci_ax2000.h
include/configs/gr_ep2s60.h
include/configs/gr_xc3s_1500.h
include/configs/grsim.h
include/configs/grsim_leon2.h
include/configs/hawkboard.h
include/configs/igep0020.h
include/configs/igep0030.h
include/configs/imx27lite-common.h
include/configs/imx31_litekit.h
include/configs/imx31_phycore.h
include/configs/innokom.h [deleted file]
include/configs/integratorap.h
include/configs/integratorcp.h
include/configs/io64.h [new file with mode: 0644]
include/configs/lacie_kw.h [moved from include/configs/netspace_v2.h with 88% similarity]
include/configs/lubbock.h
include/configs/m28evk.h [new file with mode: 0644]
include/configs/meesc.h
include/configs/microblaze-generic.h
include/configs/mx25pdk.h
include/configs/mx31ads.h
include/configs/mx31pdk.h
include/configs/mx35pdk.h
include/configs/mx51evk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/nios2-generic.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_evm_common.h
include/configs/omap3_evm_quick_mmc.h
include/configs/omap3_evm_quick_nand.h
include/configs/omap3_mvblx.h
include/configs/omap3_overo.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/omap4_common.h
include/configs/omap5_evm.h [new file with mode: 0644]
include/configs/otc570.h
include/configs/p1_p2_rdb_pc.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/pleb2.h [deleted file]
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/pm9g45.h
include/configs/pxa-common.h [new file with mode: 0644]
include/configs/pxa255_idp.h
include/configs/qong.h
include/configs/sh7757lcr.h
include/configs/sh7763rdp.h
include/configs/tny_a9260.h
include/configs/trizepsiv.h
include/configs/tt01.h
include/configs/tx25.h
include/configs/vision2.h
include/configs/vpac270.h
include/configs/xaeniax.h
include/configs/xm250.h [deleted file]
include/configs/zipitz2.h
include/configs/zmx25.h
include/dataflash.h
include/ddr_spd.h
include/environment.h
include/exports.h
include/fdt_support.h
include/gdsys_fpga.h
include/image.h
include/lcd.h
include/linux/mtd/nand.h
include/mc13892.h
include/nand.h
include/net.h
include/onenand_uboot.h
include/pca9698.h
include/sdhci.h
include/search.h
include/serial.h
include/synopsys/dwcddr21mctl.h [new file with mode: 0644]
include/tpm.h [new file with mode: 0644]
include/video_font.h
include/video_font_data.h [new file with mode: 0644]
lib/hashtable.c
lib/qsort.c
nand_spl/board/davinci/da8xxevm/Makefile
nand_spl/board/samsung/smdk6400/Makefile
nand_spl/nand_boot.c
net/bootp.c
net/net.c
net/nfs.c
net/tftp.c
onenand_ipl/board/vpac270/Makefile [deleted file]
onenand_ipl/board/vpac270/config.mk [deleted file]
post/board/lwmon5/gdc.c
post/lib_powerpc/fpu/20001122-1.c
spl/Makefile
tools/.gitignore
tools/Makefile
tools/aisimage.c
tools/bmp_logo.c
tools/checkpatch.pl [new file with mode: 0755]
tools/default_image.c
tools/env/Makefile
tools/envcrc.c
tools/mkenvimage.c [new file with mode: 0644]
tools/mxsboot.c [new file with mode: 0644]
tools/omap/clocks_get_m_n.c
tools/os_support.c
tools/os_support.h

diff --git a/.checkpatch.conf b/.checkpatch.conf
new file mode 100644 (file)
index 0000000..977db9e
--- /dev/null
@@ -0,0 +1,14 @@
+# Not Linux, so don't expect a Linux tree.
+--no-tree
+
+# Temporary for false positive in checkpatch
+--ignore COMPLEX_MACRO
+
+# For CONFIG_SYS_I2C_NOPROBES
+--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
+
+# For simple_strtoul
+--ignore CONSIDER_KSTRTO
+
+# For min/max
+--ignore MINMAX
index 70a11f7..ff4bae0 100644 (file)
@@ -36,6 +36,7 @@
 /u-boot.lds
 /u-boot.ubl
 /u-boot.dtb
+/u-boot.sb
 
 #
 # Generated files
diff --git a/CREDITS b/CREDITS
index e8e923a..dead57d 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -376,7 +376,7 @@ D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
 N: Stelian Pop
-E: stelian.pop@leadtechdesign.com
+E: stelian@popies.net
 D: Atmel AT91CAP9ADK support
 
 N: Ricardo Ribalda Delgado
index 030fe4a..2ecc664 100644 (file)
@@ -142,6 +142,10 @@ Phil Edworthy <phil.edworthy@renesas.com>
 
        rsk7264         SH7264
 
+egnite GmbH <info@egnite.de>
+
+       ethernut5       ARM926EJS (AT91SAM9XE SoC)
+
 Dirk Eibach <eibach@gdsys.de>
 
        devconcenter    PPC460EX
@@ -150,6 +154,7 @@ Dirk Eibach <eibach@gdsys.de>
        gdppc440etx     PPC440EP/GR
        intip           PPC460EX
        io              PPC405EP
+       io64            PPC405EX
        iocon           PPC405EP
        neo             PPC405EP
 
@@ -305,10 +310,6 @@ Ryan Mallon <ryan@bluewatersys.com>
        snapper9260             ARM926EJS (AT91SAM9260 SoC)
        snapper9g20             ARM926EJS (AT91SAM9G20 SoC)
 
-Eran Man <eran@nbase.co.il>
-
-       EVB64260_750CX  MPC750CX
-
 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 
        PPChameleonEVB  PPC405EP
@@ -454,6 +455,10 @@ Jon Smirl <jonsmirl@gmail.com>
 
        pcm030          MPC5200
 
+Ira W. Snyder <iws@ovro.caltech.edu>
+
+       P2020COME       P2020
+
 Timur Tabi <timur@freescale.com>
 
        MPC8349E-mITX   MPC8349
@@ -543,10 +548,10 @@ Unknown / orphaned boards:
        rsdproto        MPC8260
 
        EVB64260        MPC7xx_74xx
+       EVB64260_750CX  MPC750CX        [Eran Man <eran@nbase.co.il>]
 
        versatile       ARM926EJ-S
 
-
 #########################################################################
 # ARM Systems:                                                         #
 #                                                                      #
@@ -650,6 +655,7 @@ Simon Guinot <simon.guinot@sequanux.org>
        inetspace_v2    ARM926EJS (Kirkwood SoC)
        netspace_v2     ARM926EJS (Kirkwood SoC)
        netspace_max_v2 ARM926EJS (Kirkwood SoC)
+       net2big_v2      ARM926EJS (Kirkwood SoC)
 
 Igor Grinberg <grinberg@compulab.co.il>
 
@@ -700,20 +706,12 @@ Chander Kashyap <k.chander@samsung.com>
 Torsten Koschorrek <koschorrek@synertronixx.de>
        scb9328         ARM920T (i.MXL)
 
-Frederik Kriewitz <frederik@kriewitz.eu>
-
-       devkit8000      ARM ARMV7 (OMAP3530 SoC)
-
 Sergey Kubushyn <ksi@koi8.net>
 
        DV-EVM          ARM926EJS
        SONATA          ARM926EJS
        SCHMOOGIE       ARM926EJS
 
-Prakash Kumar <prakash@embedx.com>
-
-       cerf250         xscale/pxa
-
 Vipin Kumar <vipin.kumar@st.com>
 
        spear300        ARM926EJS (spear300 Soc)
@@ -775,17 +773,17 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
 
        omap730p2       ARM926EJS
 
-Manikandan Pillai <mani.pillai@ti.com>
-
-       omap3_evm       ARM ARMV7 (OMAP3xx SoC)
-
-Stelian Pop <stelian.pop@leadtechdesign.com>
+Stelian Pop <stelian@popies.net>
 
        at91sam9260ek   ARM926EJS (AT91SAM9260 SoC)
        at91sam9261ek   ARM926EJS (AT91SAM9261 SoC)
        at91sam9263ek   ARM926EJS (AT91SAM9263 SoC)
        at91sam9rlek    ARM926EJS (AT91SAM9RL SoC)
 
+Tom Rini <trini@ti.com>
+
+       omap3_evm       ARM ARMV7 (OMAP3xx SoC)
+
 Tom Rix <Tom.Rix@windriver.com>
 
        omap3_zoom2     ARM ARMV7 (OMAP3xx SoC)
@@ -814,14 +812,10 @@ Jens Scharsig <esw@bus-elektronik.de>
 
 Heiko Schocher <hs@denx.de>
 
+       enbw_cmc        ARM926EJS (AM1808 SoC)
        magnesium       i.MX27
        mgcoge3un       ARM926EJS (Kirkwood SoC)
 
-Robert Schwebel <r.schwebel@pengutronix.de>
-
-       csb226          xscale/pxa
-       innokom         xscale/pxa
-
 Michael Schwingen <michael@schwingen.org>
 
        actux1          xscale/ixp
@@ -850,6 +844,7 @@ Aneesh V <aneesh@ti.com>
 
        omap4_panda     ARM ARMV7 (OMAP4xx SoC)
        omap4_sdp4430   ARM ARMV7 (OMAP4xx SoC)
+       omap5_evm       ARM ARMV7 (OMAP5xx Soc)
 
 Marek Vasut <marek.vasut@gmail.com>
 
@@ -859,6 +854,7 @@ Marek Vasut <marek.vasut@gmail.com>
        palmtc          xscale/pxa
        vpac270         xscale/pxa
        zipitz2         xscale/pxa
+       m28evk          i.MX28
        efikamx         i.MX51
        efikasb         i.MX51
 
@@ -883,6 +879,10 @@ Tom Warren <twarren@nvidia.com>
        harmony         Tegra2 (ARM7 & A9 Dual Core)
        seaboard        Tegra2 (ARM7 & A9 Dual Core)
 
+Thomas Weber <weber@corscience.de>
+
+       devkit8000      ARM ARMV7 (OMAP3530 SoC)
+
 Lei Wen <leiwen@marvell.com>
 
        dkb             ARM926EJS (PANTHEON 88AP920 SOC)
@@ -906,7 +906,6 @@ Sughosh Ganu <urwithsughosh@gmail.com>
 Unknown / orphaned boards:
        Board           CPU     Last known maintainer / Comment
 .........................................................................
-       cradle          xscale/pxa      Kyle Harris <kharris@nexus-tech.net> / dead address
        lubbock         xscale/pxa      Kyle Harris <kharris@nexus-tech.net> / dead address
 
        imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
@@ -1056,6 +1055,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
        RSK7203         SH7203
        AP325RXA        SH7723
        SHMIN           SH7706
+       ECOVEC          SH7724
 
 Mark Jonas <mark.jonas@de.bosch.com>
 
@@ -1151,6 +1151,7 @@ Chong Huang <chuang@ucrobotics.com>
 Macpaul Lin <macpaul@andestech.com>
 
        ADP-AG101       N1213 (AG101 SoC)
+       ADP-AG101P      N1213 (AG101P XC5 FPGA)
 
 #########################################################################
 # End of MAINTAINERS list                                              #
diff --git a/MAKEALL b/MAKEALL
index 95b7cd3..fa0121c 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -16,6 +16,7 @@ usage()
          -c CPU,    --cpu CPU         Build all boards with cpu CPU
          -v VENDOR, --vendor VENDOR   Build all boards with vendor VENDOR
          -s SOC,    --soc SOC         Build all boards with soc SOC
+         -l,        --list            List all targets to be built
          -h,        --help            This help output
 
        Selections by these options are logically ANDed; if the same option
@@ -47,8 +48,8 @@ usage()
        exit ${ret}
 }
 
-SHORT_OPTS="ha:c:v:s:"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:"
+SHORT_OPTS="ha:c:v:s:l"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
@@ -65,6 +66,7 @@ TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \
 eval set -- "$TEMP"
 
 SELECTED=''
+ONLY_LIST=''
 
 while true ; do
        case "$1" in
@@ -104,6 +106,9 @@ while true ; do
                fi
                SELECTED='y'
                shift 2 ;;
+       -l|--list)
+               ONLY_LIST='y'
+               shift ;;
        -h|--help)
                usage ;;
        --)
@@ -316,7 +321,6 @@ LIST_ARM11="$(boards_by_cpu arm1136)        \
        imx31_phycore           \
        imx31_phycore_eet       \
        mx31pdk                 \
-       mx31pdk_nand            \
        smdk6400                \
 "
 
@@ -488,6 +492,11 @@ LIST_nds32="$(boards_by_arch nds32)"
 build_target() {
        target=$1
 
+       if [ "$ONLY_LIST" == 'y' ] ; then
+               echo "$target"
+               return
+       fi
+
        ${MAKE} distclean >/dev/null
        ${MAKE} -s ${target}_config
 
@@ -531,6 +540,7 @@ build_targets() {
 #-----------------------------------------------------------------------
 
 print_stats() {
+       if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
        echo ""
        echo "--------------------- SUMMARY ----------------------------"
        echo "Boards compiled: ${TOTAL_CNT}"
index 5017f3b..de65a17 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -277,6 +277,9 @@ LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 LIBS += drivers/rtc/librtc.o
 LIBS += drivers/serial/libserial.o
+ifeq ($(CONFIG_GENERIC_LPC_TPM),y)
+LIBS += drivers/tpm/libtpm.o
+endif
 LIBS += drivers/twserial/libtws.o
 LIBS += drivers/usb/eth/libusb_eth.o
 LIBS += drivers/usb/gadget/libusb_gadget.o
@@ -290,16 +293,9 @@ LIBS += lib/libfdt/libfdt.o
 LIBS += api/libapi.o
 LIBS += post/libpost.o
 
-ifeq ($(SOC),am33xx)
-LIBS += $(CPUDIR)/omap-common/libomap-common.o
-endif
-ifeq ($(SOC),omap3)
-LIBS += $(CPUDIR)/omap-common/libomap-common.o
-endif
-ifeq ($(SOC),omap4)
+ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS += $(CPUDIR)/omap-common/libomap-common.o
 endif
-
 ifeq ($(SOC),s5pc1xx)
 LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
@@ -424,6 +420,10 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
                rm $(obj)u-boot-ubl.bin
                rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
+               elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
+                       -o $(obj)u-boot.sb
+
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \
                cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@@ -486,7 +486,7 @@ mmc_spl:    $(TIMESTAMP_FILE) $(VERSION_FILE) depend
 
 $(obj)mmc_spl/u-boot-mmc-spl.bin:      mmc_spl
 
-$(obj)spl/u-boot-spl.bin:              depend
+$(obj)spl/u-boot-spl.bin:      $(SUBDIR_TOOLS) depend
                $(MAKE) -C spl all
 
 updater:
@@ -754,7 +754,7 @@ clean:
               $(obj)tools/envcrc                                         \
               $(obj)tools/gdb/{astest,gdbcont,gdbsend}                   \
               $(obj)tools/gen_eth_addr    $(obj)tools/img2srec           \
-              $(obj)tools/mkimage         $(obj)tools/mpc86x_clk         \
+              $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk         \
               $(obj)tools/ncb             $(obj)tools/ubsha1
        @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}        \
               $(obj)board/matrix_vision/*/bootscript.img                 \
@@ -763,6 +763,7 @@ clean:
               $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]          \
               $(obj)arch/blackfin/cpu/init.{lds,elf}
        @rm -f $(obj)include/bmp_logo.h
+       @rm -f $(obj)include/bmp_logo_data.h
        @rm -f $(obj)lib/asm-offsets.s
        @rm -f $(obj)include/generated/asm-offsets.h
        @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@@ -779,11 +780,14 @@ clean:
                -o -name '*.o'  -o -name '*.a' -o -name '*.exe' \) -print \
                | xargs rm -f
 
-clobber:       clean
-       @find $(OBJTREE) -type f \( -name '*.depend*' \
-               -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-               -print0 \
-               | xargs -0 rm -f
+# Removes everything not needed for testing u-boot
+tidy:  clean
+       @find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f
+
+clobber:       tidy
+       @find $(OBJTREE) -type f \( -name '*.srec' \
+               -o -name '*.bin' -o -name u-boot.img \) \
+               -print0 | xargs -0 rm -f
        @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
                $(obj)cscope.* $(obj)*.*~
        @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@@ -791,7 +795,8 @@ clobber:    clean
        @rm -f $(obj)u-boot.imx
        @rm -f $(obj)u-boot.ubl
        @rm -f $(obj)u-boot.dtb
-       @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
+       @rm -f $(obj)u-boot.sb
+       @rm -f $(obj)tools/inca-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
        @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
        @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
diff --git a/README b/README
index 73ca042..3ddec77 100644 (file)
--- a/README
+++ b/README
@@ -1027,6 +1027,12 @@ The following options need to be configured:
                        Define this to use i/o functions instead of macros
                        (some hardware wont work with macros)
 
+               CONFIG_DRIVER_TI_EMAC
+               Support for davinci emac
+
+                       CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+                       Define this if you have more then 3 PHYs.
+
                CONFIG_FTGMAC100
                Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
 
@@ -1066,6 +1072,16 @@ The following options need to be configured:
                        CONFIG_SH_ETHER_CACHE_WRITEBACK
                        If this option is set, the driver enables cache flush.
 
+- TPM Support:
+               CONFIG_GENERIC_LPC_TPM
+               Support for generic parallel port TPM devices. Only one device
+               per system is supported at this time.
+
+                       CONFIG_TPM_TIS_BASE_ADDRESS
+                       Base address where the generic TPM device is mapped
+                       to. Contemporary x86 systems usually map it at
+                       0xfed40000.
+
 - USB Support:
                At the moment only the UHCI host controller is
                supported (PIP405, MIP405, MPC5200); define
@@ -3268,6 +3284,44 @@ Low Level (hardware related) configuration options:
                be used if available. These functions may be faster under some
                conditions but may increase the binary size.
 
+Freescale QE/FMAN Firmware Support:
+-----------------------------------
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of "firmware", which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+       The address in the storage device where the firmware is located.  The
+       meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+       is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+       The maximum possible size of the firmware.  The firmware binary format
+       has a field that specifies the actual size of the firmware, but it
+       might not be possible to read any part of the firmware unless some
+       local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+       Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+       normal addressable memory via the LBC.  CONFIG_SYS_FMAN_FW_ADDR is the
+       virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+       Specifies that QE/FMAN firmware is located in NAND flash.
+       CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+       Specifies that QE/FMAN firmware is located on the primary SD/MMC
+       device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+       Specifies that QE/FMAN firmware is located on the primary SPI
+       device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
 Building the Software:
 ======================
 
index 2a64c4d..0e99f74 100644 (file)
@@ -24,7 +24,8 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)libapi.o
 
-COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
+COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
+                      api_platform-$(ARCH).o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
index 853f010..a3bf60a 100644 (file)
--- a/api/api.c
+++ b/api/api.c
@@ -553,6 +553,50 @@ static int API_env_enum(va_list ap)
        return 0;
 }
 
+/*
+ * pseudo signature:
+ *
+ * int API_display_get_info(int type, struct display_info *di)
+ */
+static int API_display_get_info(va_list ap)
+{
+       int type;
+       struct display_info *di;
+
+       type = va_arg(ap, int);
+       di = va_arg(ap, struct display_info *);
+
+       return display_get_info(type, di);
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_display_draw_bitmap(ulong bitmap, int x, int y)
+ */
+static int API_display_draw_bitmap(va_list ap)
+{
+       ulong bitmap;
+       int x, y;
+
+       bitmap = va_arg(ap, ulong);
+       x = va_arg(ap, int);
+       y = va_arg(ap, int);
+
+       return display_draw_bitmap(bitmap, x, y);
+}
+
+/*
+ * pseudo signature:
+ *
+ * void API_display_clear(void)
+ */
+static int API_display_clear(va_list ap)
+{
+       display_clear();
+       return 0;
+}
+
 static cfp_t calls_table[API_MAXCALL] = { NULL, };
 
 /*
@@ -616,6 +660,9 @@ void api_init(void)
        calls_table[API_ENV_GET] = &API_env_get;
        calls_table[API_ENV_SET] = &API_env_set;
        calls_table[API_ENV_ENUM] = &API_env_enum;
+       calls_table[API_DISPLAY_GET_INFO] = &API_display_get_info;
+       calls_table[API_DISPLAY_DRAW_BITMAP] = &API_display_draw_bitmap;
+       calls_table[API_DISPLAY_CLEAR] = &API_display_clear;
        calls_no = API_MAXCALL;
 
        debugf("API initialized with %d calls\n", calls_no);
diff --git a/api/api_display.c b/api/api_display.c
new file mode 100644 (file)
index 0000000..6439170
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <api_public.h>
+#include <lcd.h>
+#include <video_font.h> /* Get font width and height */
+
+/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+#include <bmp_logo.h>
+#endif
+
+/* TODO(clchiou): add support of video device */
+
+int display_get_info(int type, struct display_info *di)
+{
+       if (!di)
+               return API_EINVAL;
+
+       switch (type) {
+       default:
+               debug("%s: unsupport display device type: %d\n",
+                               __FILE__, type);
+               return API_ENODEV;
+#ifdef CONFIG_LCD
+       case DISPLAY_TYPE_LCD:
+               di->pixel_width  = panel_info.vl_col;
+               di->pixel_height = panel_info.vl_row;
+               di->screen_rows = CONSOLE_ROWS;
+               di->screen_cols = CONSOLE_COLS;
+               break;
+#endif
+       }
+
+       di->type = type;
+       return 0;
+}
+
+int display_draw_bitmap(ulong bitmap, int x, int y)
+{
+       if (!bitmap)
+               return API_EINVAL;
+#ifdef CONFIG_LCD
+       return lcd_display_bitmap(bitmap, x, y);
+#else
+       return API_ENODEV;
+#endif
+}
+
+void display_clear(void)
+{
+#ifdef CONFIG_LCD
+       lcd_clear();
+#endif
+}
index 94a7fc5..988f702 100644 (file)
@@ -45,4 +45,8 @@ int           dev_write_net(void *, void *, int);
 
 void dev_stor_init(void);
 
+int display_get_info(int type, struct display_info *di);
+int display_draw_bitmap(ulong bitmap, int x, int y);
+void display_clear(void);
+
 #endif /* _API_PRIVATE_H_ */
index b42dac3..2ebee2e 100644 (file)
@@ -27,7 +27,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 
-#ifdef CONFIG_SYS_MX31_UART1
 void mx31_uart1_hw_init(void)
 {
        /* setup pins for UART1 */
@@ -36,9 +35,7 @@ void mx31_uart1_hw_init(void)
        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 }
-#endif
 
-#ifdef CONFIG_SYS_MX31_UART2
 void mx31_uart2_hw_init(void)
 {
        /* setup pins for UART2 */
@@ -47,7 +44,6 @@ void mx31_uart2_hw_init(void)
        mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
        mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
 }
-#endif
 
 #ifdef CONFIG_MXC_SPI
 /*
index 4f27e25..f458281 100644 (file)
@@ -27,8 +27,6 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
-#define IOMUXGPR       (IOMUXC_BASE + 0x008)
-
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
        u32 mfi = GET_PLL_MFI(reg);
@@ -89,7 +87,7 @@ static u32 mx31_get_hsp_clk(void)
 void mx31_dump_clocks(void)
 {
        u32 cpufreq = mx31_get_mcu_main_clk();
-       printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
+       printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
        printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
        printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
 }
@@ -146,14 +144,15 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 void mx31_set_gpr(enum iomux_gp_func gp, char en)
 {
        u32 l;
+       struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
 
-       l = readl(IOMUXGPR);
+       l = readl(&iomuxc->gpr);
        if (en)
                l |= gp;
        else
                l &= ~gp;
 
-       writel(l, IOMUXGPR);
+       writel(l, &iomuxc->gpr);
 }
 
 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
@@ -216,7 +215,7 @@ static char *get_reset_cause(void)
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
+int print_cpuinfo(void)
 {
        u32 srev = get_cpu_rev();
 
index 443d31d..4bfcef2 100644 (file)
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <faraday/ftpmu010.h>
 #include <faraday/fttmr010.h>
 
-static ulong timestamp;
-static ulong lastdec;
-
-static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+DECLARE_GLOBAL_DATA_PTR;
 
 #define TIMER_CLOCK    32768
 #define TIMER_LOAD_VAL 0xffffffff
 
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+       tick *= CONFIG_SYS_HZ;
+       do_div(tick, gd->timer_rate_hz);
+
+       return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+       usec *= gd->timer_rate_hz;
+       do_div(usec, 1000000);
+
+       return usec;
+}
+
 int timer_init(void)
 {
+       struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
        unsigned int cr;
 
        debug("%s()\n", __func__);
@@ -59,106 +74,57 @@ int timer_init(void)
        cr |= FTTMR010_TM3_ENABLE;
        writel(cr, &tmr->cr);
 
-       /* init the timestamp and lastdec value */
-       reset_timer_masked();
+       gd->timer_rate_hz = TIMER_CLOCK;
+       gd->tbu = gd->tbl = 0;
 
        return 0;
 }
 
 /*
- * timer without interrupts
- */
-
-/*
- * reset time
- */
-void reset_timer_masked(void)
-{
-       /* capure current decrementer value time */
-       lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-       timestamp = 0;          /* start "advancing" time stamp from 0 */
-
-       debug("%s(): lastdec = %lx\n", __func__, lastdec);
-}
-
-/*
- * return timer ticks
- */
-ulong get_timer_masked(void)
-{
-       /* current tick value */
-       ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
-       debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
-
-       if (lastdec >= now) {
-               /*
-                * normal mode (non roll)
-                * move stamp fordward with absoulte diff ticks
-                */
-               timestamp += lastdec - now;
-       } else {
-               /*
-                * we have overflow of the count down timer
-                *
-                * nts = ts + ld + (TLV - now)
-                * ts=old stamp, ld=time that passed before passing through -1
-                * (TLV-now) amount of time after passing though -1
-                * nts = new "advancing time stamp"...it could also roll and
-                * cause problems.
-                */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-
-       lastdec = now;
-
-       debug("%s() returns %lx\n", __func__, timestamp);
-
-       return timestamp;
-}
-
-/*
- * return difference between timer ticks and base
+ * Get the current 64 bit timer tick count
  */
-ulong get_timer(ulong base)
+unsigned long long get_ticks(void)
 {
-       debug("%s(%lx)\n", __func__, base);
-       return get_timer_masked() - base;
+       struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+       ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
+
+       /* increment tbu if tbl has rolled over */
+       if (now < gd->tbl)
+               gd->tbu++;
+       gd->tbl = now;
+       return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
 }
 
-/* delay x useconds AND preserve advance timestamp value */
 void __udelay(unsigned long usec)
 {
-       long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-       unsigned long now, last = readl(&tmr->timer3_counter);
-
-       debug("%s(%lu)\n", __func__, usec);
-       while (tmo > 0) {
-               now = readl(&tmr->timer3_counter);
-               if (now > last) /* count down timer overflow */
-                       tmo -= TIMER_LOAD_VAL + last - now;
-               else
-                       tmo -= last - now;
-               last = now;
-       }
+       unsigned long long start;
+       ulong tmo;
+
+       start = get_ticks();            /* get current timestamp */
+       tmo = usec_to_tick(usec);       /* convert usecs to ticks */
+       while ((get_ticks() - start) < tmo)
+               ;                       /* loop till time has passed */
 }
 
 /*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
  */
-unsigned long long get_ticks(void)
+ulong get_timer(ulong base)
 {
-       debug("%s()\n", __func__);
-       return get_timer(0);
+       return tick_to_time(get_ticks()) - base;
 }
 
 /*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * Return the number of timer ticks per second.
  */
 ulong get_tbclk(void)
 {
-       debug("%s()\n", __func__);
-       return CONFIG_SYS_HZ;
+       return gd->timer_rate_hz;
 }
index 412f502..4caa157 100644 (file)
@@ -5,7 +5,7 @@
  * Andreas BieƟmann <andreas.devel@googlemail.com>
  *
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index 930e0d1..5923e65 100644 (file)
@@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)lib$(CPU).o
 
 START  = start.o
-COBJS  = cpu.o
+COBJS  = cpu.o cache.o
+
+ifdef  CONFIG_SPL_BUILD
+ifdef  CONFIG_SPL_NO_CPU_SUPPORT_CODE
+START  :=
+endif
+endif
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
index 2d878fd..db2ecb8 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * (C) Copyright 2009
index 65b8d51..a4e9f09 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index edc7972..ae8cd56 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index 6eb0f30..7191db2 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * (C) Copyright 2009-2011
index 5ff32e3..f31c364 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index b0a1687..ca44cf5 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index 6e59c86..a1bb28d 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index 023719a..f6a7cb7 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
index a087687..f70ce83 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644 (file)
index 0000000..4415642
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2011
+ * Ilya Yanok, EmCraft Systems
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <linux/types.h>
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static inline void dcache_noop(void)
+{
+       if (dcache_status()) {
+               puts("WARNING: cache operations are not implemented!\n"
+                    "WARNING: disabling D-Cache now, you can re-enable it"
+                    "later with 'dcache on' command\n");
+               dcache_disable();
+       }
+}
+
+void invalidate_dcache_all(void)
+{
+       dcache_noop();
+}
+
+void flush_dcache_all(void)
+{
+       dcache_noop();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+       dcache_noop();
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+       dcache_noop();
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void  flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
index 98c7e55..5ae89df 100644 (file)
@@ -27,12 +27,13 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS-y                                += cpu.o timer.o psc.o
-COBJS-$(CONFIG_AM18018_LOWLEVEL)       += am1808_lowlevel.o
+COBJS-y                                += cpu.o misc.o timer.o psc.o pinmux.o
+COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
 COBJS-$(CONFIG_SOC_DM355)      += dm355.o
 COBJS-$(CONFIG_SOC_DM365)      += dm365.o
 COBJS-$(CONFIG_SOC_DM644X)     += dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)     += dm646x.o
+COBJS-$(CONFIG_SOC_DA850)      += da850_pinmux.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
deleted file mode 100644 (file)
index 1ea4a9f..0000000
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * SoC-specific lowlevel code for AM1808 and similar chips
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/arch/am1808_lowlevel.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/emif_defs.h>
-
-void am1808_waitloop(unsigned long loopcnt)
-{
-       unsigned long   i;
-
-       for (i = 0; i < loopcnt; i++)
-               asm("   NOP");
-}
-
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
-{
-       if (reg == davinci_pllc0_regs)
-               /* Unlock PLL registers. */
-               clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
-
-       /*
-        * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
-        * through MMR
-        */
-       clrbits_le32(&reg->pllctl, 0x00000020);
-       /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
-       clrbits_le32(&reg->pllctl, 0x00000200);
-
-       /* Set PLLEN=0 => PLL BYPASS MODE */
-       clrbits_le32(&reg->pllctl, 0x00000001);
-
-       am1808_waitloop(150);
-
-       if (reg == davinci_pllc0_regs) {
-               /*
-                * Select the Clock Mode bit 8 as External Clock or On Chip
-                * Oscilator
-                */
-               dv_maskbits(&reg->pllctl, 0xFFFFFEFF);
-               setbits_le32(&reg->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
-       }
-
-       /* Clear PLLRST bit to reset the PLL */
-       clrbits_le32(&reg->pllctl, 0x00000008);
-
-       /* Disable the PLL output */
-       setbits_le32(&reg->pllctl, 0x00000010);
-
-       /* PLL initialization sequence */
-       /*
-        * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
-        * power down bit
-        */
-       clrbits_le32(&reg->pllctl, 0x00000002);
-
-       /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
-       clrbits_le32(&reg->pllctl, 0x00000010);
-
-       /* Program the required multiplier value in PLLM */
-       writel(pllmult, &reg->pllm);
-
-       /* program the postdiv */
-       if (reg == davinci_pllc0_regs)
-               writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
-                       &reg->postdiv);
-       else
-               writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
-                       &reg->postdiv);
-
-       /*
-        * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
-        * no GO operation is currently in progress
-        */
-       while ((readl(&reg->pllstat) & 0x1) == 1)
-               ;
-
-       if (reg == davinci_pllc0_regs) {
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, &reg->plldiv1);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, &reg->plldiv2);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, &reg->plldiv3);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, &reg->plldiv4);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, &reg->plldiv5);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, &reg->plldiv6);
-               writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, &reg->plldiv7);
-       } else {
-               writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, &reg->plldiv1);
-               writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, &reg->plldiv2);
-               writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, &reg->plldiv3);
-       }
-
-       /*
-        * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
-        * transition.
-        */
-       setbits_le32(&reg->pllcmd, 0x01);
-
-       /*
-        * Wait for the GOSTAT bit in PLLSTAT to clear to 0
-        * (completion of phase alignment).
-        */
-       while ((readl(&reg->pllstat) & 0x1) == 1)
-               ;
-
-       /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
-       am1808_waitloop(200);
-
-       /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
-       setbits_le32(&reg->pllctl, 0x00000008);
-
-       /* Wait for PLL to lock. See PLL spec for PLL lock time */
-       am1808_waitloop(2400);
-
-       /*
-        * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
-        * mode
-        */
-       setbits_le32(&reg->pllctl, 0x00000001);
-
-
-       /*
-        * clear EMIFA and EMIFB clock source settings, let them
-        * run off SYSCLK
-        */
-       if (reg == davinci_pllc0_regs)
-               dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
-
-       return 0;
-}
-
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
-               unsigned char domain, unsigned char state)
-{
-       struct davinci_psc_regs *reg;
-       dv_reg_p mdstat, mdctl;
-
-       if (pscnum == 0) {
-               reg = davinci_psc0_regs;
-               mdstat = &reg->psc0.mdstat[module];
-               mdctl = &reg->psc0.mdctl[module];
-       } else {
-               reg = davinci_psc1_regs;
-               mdstat = &reg->psc1.mdstat[module];
-               mdctl = &reg->psc1.mdctl[module];
-       }
-
-       /* Wait for any outstanding transition to complete */
-       while ((readl(&reg->ptstat) & (0x00000001 << domain)))
-               ;
-
-       /* If we are already in that state, just return */
-       if ((readl(mdstat) & 0x1F) == state)
-               return;
-
-       /* Perform transition */
-       writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
-       setbits_le32(&reg->ptcmd, (0x00000001 << domain));
-
-       /* Wait for transition to complete */
-       while (readl(&reg->ptstat) & (0x00000001 << domain))
-               ;
-
-       /* Wait and verify the state */
-       while ((readl(mdstat) & 0x1F) != state)
-               ;
-}
-
-int am1808_ddr_setup(unsigned int freq)
-{
-       unsigned long   tmp;
-
-       /* Enable the Clock to DDR2/mDDR */
-       am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
-
-       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-       if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
-               /* Begin VTP Calibration */
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-
-               /* Polling READY bit to see when VTP calibration is done */
-               tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-               while ((tmp & VTP_READY) != VTP_READY)
-                       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
-       }
-
-       writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-       clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
-               (1 << DDR_SLEW_CMOSEN_BIT));
-
-       setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
-
-       writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
-               (readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
-               &dv_ddr2_regs_ctrl->sdbcr);
-       writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
-
-       writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-       writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
-       clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
-               (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
-
-       /*
-        * LPMODEN and MCLKSTOPEN must be set!
-        * Without this bits set, PSC don;t switch states !!
-        */
-       writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
-               (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
-               (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
-               &dv_ddr2_regs_ctrl->sdrcr);
-
-       /* SyncReset the Clock to EMIF3A SDRAM */
-       am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
-       /* Enable the Clock to EMIF3A SDRAM */
-       am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
-
-       /* disable self refresh */
-       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
-       writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
-
-       return 0;
-}
-
-static void am1808_set_mdctl(dv_reg_p mdctl)
-{
-       if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
-               writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
-}
-
-void am1808_psc_init(void)
-{
-       struct davinci_psc_regs *reg;
-       int i;
-
-       /* PSC 0 domain 0 init */
-       reg = davinci_psc0_regs;
-       while ((readl(&reg->ptstat) & 0x00000001))
-               ;
-
-       for (i = 3; i <= 4 ; i++)
-               am1808_set_mdctl(&reg->psc0.mdctl[i]);
-
-       for (i = 7; i <= 12 ; i++)
-               am1808_set_mdctl(&reg->psc0.mdctl[i]);
-
-       /* Do Always-On Power Domain Transitions */
-       setbits_le32(&reg->ptcmd, 0x00000001);
-       while (readl(&reg->ptstat) & 0x00000001)
-               ;
-
-       /* PSC1, domain 1 init */
-       reg = davinci_psc1_regs;
-       while ((readl(&reg->ptstat) & 0x00000001))
-               ;
-
-       am1808_set_mdctl(&reg->psc1.mdctl[3]);
-       am1808_set_mdctl(&reg->psc1.mdctl[6]);
-
-       /* UART1 + UART2 */
-       for (i = 12 ; i <= 13 ; i++)
-               am1808_set_mdctl(&reg->psc1.mdctl[i]);
-
-       am1808_set_mdctl(&reg->psc1.mdctl[26]);
-       am1808_set_mdctl(&reg->psc1.mdctl[31]);
-
-       /* Do Always-On Power Domain Transitions */
-       setbits_le32(&reg->ptcmd, 0x00000001);
-       while (readl(&reg->ptstat) & 0x00000001)
-               ;
-}
-
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
-       unsigned long value)
-{
-       clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
-       setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
-       return;
-}
-
-#if defined(CONFIG_NAND_SPL)
-void nand_boot(void)
-{
-       __attribute__((noreturn)) void (*uboot)(void);
-
-       /* copy image from NOR to RAM */
-       memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
-               (void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
-               CONFIG_SYS_NAND_U_BOOT_SIZE);
-
-       /* and jump to it ... */
-       uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
-       (*uboot)();
-}
-#endif
-
-#if defined(CONFIG_NAND_SPL)
-void board_init_f(ulong bootflag)
-#else
-int arch_cpu_init(void)
-#endif
-{
-       /*
-        * copied from arch/arm/cpu/arm926ejs/start.S
-        *
-        * flush v4 I/D caches
-        */
-       asm("mov        r0, #0");
-       asm("mcr        p15, 0, r0, c7, c7, 0");        /* flush v3/v4 cache */
-       asm("mcr        p15, 0, r0, c8, c7, 0");        /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       asm("mrc        p15, 0, r0, c1, c0, 0");
-       /* clear bits 13, 9:8 (--V- --RS) */
-       asm("bic        r0, r0, #0x00002300");
-       /* clear bits 7, 2:0 (B--- -CAM) */
-       asm("bic        r0, r0, #0x00000087");
-       /* set bit 2 (A) Align */
-       asm("orr        r0, r0, #0x00000002");
-       /* set bit 12 (I) I-Cache */
-       asm("orr        r0, r0, #0x00001000");
-       asm("mcr        p15, 0, r0, c1, c0, 0");
-
-       /* Unlock kick registers */
-       writel(0x83e70b13, &davinci_syscfg_regs->kick0);
-       writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
-
-       dv_maskbits(&davinci_syscfg_regs->suspsrc,
-               ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
-
-       /* System PSC setup - enable all */
-       am1808_psc_init();
-
-       /* Setup Pinmux */
-       am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
-       am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
-       am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
-       am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
-       am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
-       am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
-       am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
-       am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
-       am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
-       am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
-       am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
-       am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
-       am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
-       am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
-       am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
-       am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
-       am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
-       am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
-       am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
-       am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
-
-       /* PLL setup */
-       am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
-       am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
-
-       /* GPIO setup */
-       board_gpio_init();
-
-       /* setup CSn config */
-       writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
-       writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
-
-       am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
-       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
-                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
-       /*
-        * Fix Power and Emulation Management Register
-        * see sprufw3a.pdf page 37 Table 24
-        */
-       writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
-               (CONFIG_SYS_NS16550_COM1 + 0x30));
-#if defined(CONFIG_NAND_SPL)
-       puts("ddr init\n");
-       am1808_ddr_setup(132);
-
-       puts("boot u-boot ...\n");
-
-       nand_boot();
-#else
-       am1808_ddr_setup(132);
-       return 0;
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
new file mode 100644 (file)
index 0000000..a532f8a
--- /dev/null
@@ -0,0 +1,291 @@
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/pll_defs.h>
+
+void da850_waitloop(unsigned long loopcnt)
+{
+       unsigned long   i;
+
+       for (i = 0; i < loopcnt; i++)
+               asm("   NOP");
+}
+
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+{
+       if (reg == davinci_pllc0_regs)
+               /* Unlock PLL registers. */
+               clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
+
+       /*
+        * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
+        * through MMR
+        */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
+       /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
+       clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
+
+       /* Set PLLEN=0 => PLL BYPASS MODE */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+       da850_waitloop(150);
+
+       if (reg == davinci_pllc0_regs) {
+               /*
+                * Select the Clock Mode bit 8 as External Clock or On Chip
+                * Oscilator
+                */
+               dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
+               setbits_le32(&reg->pllctl,
+                       (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
+       }
+
+       /* Clear PLLRST bit to reset the PLL */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+       /* Disable the PLL output */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+       /* PLL initialization sequence */
+       /*
+        * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
+        * power down bit
+        */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
+
+       /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+       /* Program the required multiplier value in PLLM */
+       writel(pllmult, &reg->pllm);
+
+       /* program the postdiv */
+       if (reg == davinci_pllc0_regs)
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
+                       &reg->postdiv);
+       else
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
+                       &reg->postdiv);
+
+       /*
+        * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
+        * no GO operation is currently in progress
+        */
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+               ;
+
+       if (reg == davinci_pllc0_regs) {
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
+       } else {
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
+       }
+
+       /*
+        * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
+        * transition.
+        */
+       setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
+
+       /*
+        * Wait for the GOSTAT bit in PLLSTAT to clear to 0
+        * (completion of phase alignment).
+        */
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+               ;
+
+       /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
+       da850_waitloop(200);
+
+       /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+       /* Wait for PLL to lock. See PLL spec for PLL lock time */
+       da850_waitloop(2400);
+
+       /*
+        * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
+        * mode
+        */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+
+       /*
+        * clear EMIFA and EMIFB clock source settings, let them
+        * run off SYSCLK
+        */
+       if (reg == davinci_pllc0_regs)
+               dv_maskbits(&davinci_syscfg_regs->cfgchip3,
+                       ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
+
+       return 0;
+}
+
+int da850_ddr_setup(void)
+{
+       unsigned long   tmp;
+
+       /* Enable the Clock to DDR2/mDDR */
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+       if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
+               /* Begin VTP Calibration */
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+
+               /* Polling READY bit to see when VTP calibration is done */
+               tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+               while ((tmp & VTP_READY) != VTP_READY)
+                       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
+       }
+
+       writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+       clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+               (1 << DDR_SLEW_CMOSEN_BIT));
+
+       /*
+        * SDRAM Configuration Register (SDCR):
+        * First set the BOOTUNLOCK bit to make configuration bits
+        * writeable.
+        */
+       setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
+
+       /*
+        * Write the new value of these bits and clear BOOTUNLOCK.
+        * At the same time, set the TIMUNLOCK bit to allow changing
+        * the timing registers
+        */
+       tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+       tmp &= ~DV_DDR_BOOTUNLOCK;
+       tmp |= DV_DDR_TIMUNLOCK;
+       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+       /* write memory configuration and timing */
+       writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+       writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+       writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+       /* clear the TIMUNLOCK bit and write the value of the CL field */
+       tmp &= ~DV_DDR_TIMUNLOCK;
+       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+       /*
+        * LPMODEN and MCLKSTOPEN must be set!
+        * Without this bits set, PSC don;t switch states !!
+        */
+       writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+               (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
+               (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
+               &dv_ddr2_regs_ctrl->sdrcr);
+
+       /* SyncReset the Clock to EMIF3A SDRAM */
+       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+       /* Enable the Clock to EMIF3A SDRAM */
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       /* disable self refresh */
+       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
+               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+       writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+       return 0;
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+       return;
+}
+
+/* pinmux_resource[] vector is defined in the board specific file */
+extern const struct pinmux_resource pinmuxes[];
+extern const int pinmuxes_size;
+
+int arch_cpu_init(void)
+{
+       /* Unlock kick registers */
+       writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+       writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+       dv_maskbits(&davinci_syscfg_regs->suspsrc,
+               CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+
+       /* configure pinmux settings */
+       if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
+               return 1;
+
+       /* PLL setup */
+       da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
+       da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+
+       /* GPIO setup */
+       board_gpio_init();
+
+       /* setup CSn config */
+#if defined(CONFIG_SYS_DA850_CS2CFG)
+       writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+#endif
+#if defined(CONFIG_SYS_DA850_CS3CFG)
+       writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
+#endif
+
+       lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
+       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+       /*
+        * Fix Power and Emulation Management Register
+        * see sprufw3a.pdf page 37 Table 24
+        */
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+              &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+       da850_ddr_setup();
+       return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
new file mode 100644 (file)
index 0000000..fa07fb5
--- /dev/null
@@ -0,0 +1,171 @@
+/*
+ * Pinmux configurations for the DA850 SoCs
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI pin muxer settings */
+const struct pinmux_config spi1_pins_base[] = {
+       { pinmux(5), 1, 2 }, /* SPI1_CLK */
+       { pinmux(5), 1, 4 }, /* SPI1_SOMI */
+       { pinmux(5), 1, 5 }, /* SPI1_SIMO */
+};
+
+const struct pinmux_config spi1_pins_scs0[] = {
+       { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
+};
+
+/* UART pin muxer settings */
+const struct pinmux_config uart1_pins_txrx[] = {
+       { pinmux(4), 2, 6 }, /* UART1_RXD */
+       { pinmux(4), 2, 7 }, /* UART1_TXD */
+};
+
+const struct pinmux_config uart2_pins_txrx[] = {
+       { pinmux(4), 2, 4 }, /* UART2_RXD */
+       { pinmux(4), 2, 5 }, /* UART2_TXD */
+};
+
+const struct pinmux_config uart2_pins_rtscts[] = {
+       { pinmux(0), 4, 6 }, /* UART2_RTS */
+       { pinmux(0), 4, 7 }, /* UART2_CTS */
+};
+
+/* EMAC pin muxer settings*/
+const struct pinmux_config emac_pins_rmii[] = {
+       { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
+       { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
+       { pinmux(14), 8, 4 }, /* RMII_TXEN */
+       { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
+       { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
+       { pinmux(14), 8, 7 }, /* RMII_RXER */
+       { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
+};
+
+const struct pinmux_config emac_pins_mii[] = {
+       { pinmux(2), 8, 1 }, /* MII_TXEN */
+       { pinmux(2), 8, 2 }, /* MII_TXCLK */
+       { pinmux(2), 8, 3 }, /* MII_COL */
+       { pinmux(2), 8, 4 }, /* MII_TXD[3] */
+       { pinmux(2), 8, 5 }, /* MII_TXD[2] */
+       { pinmux(2), 8, 6 }, /* MII_TXD[1] */
+       { pinmux(2), 8, 7 }, /* MII_TXD[0] */
+       { pinmux(3), 8, 0 }, /* MII_RXCLK */
+       { pinmux(3), 8, 1 }, /* MII_RXDV */
+       { pinmux(3), 8, 2 }, /* MII_RXER */
+       { pinmux(3), 8, 3 }, /* MII_CRS */
+       { pinmux(3), 8, 4 }, /* MII_RXD[3] */
+       { pinmux(3), 8, 5 }, /* MII_RXD[2] */
+       { pinmux(3), 8, 6 }, /* MII_RXD[1] */
+       { pinmux(3), 8, 7 }, /* MII_RXD[0] */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+       { pinmux(4), 8, 0 }, /* MDIO_CLK */
+       { pinmux(4), 8, 1 }, /* MDIO_D */
+};
+
+/* I2C pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+       { pinmux(4), 2, 2 }, /* I2C0_SCL */
+       { pinmux(4), 2, 3 }, /* I2C0_SDA */
+};
+
+const struct pinmux_config i2c1_pins[] = {
+       { pinmux(4), 4, 4 }, /* I2C1_SCL */
+       { pinmux(4), 4, 5 }, /* I2C1_SDA */
+};
+
+/* EMIFA pin muxer settings */
+const struct pinmux_config emifa_pins_cs2[] = {
+       { pinmux(7), 1, 0 }, /* EMA_CS2 */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+       { pinmux(7), 1, 1 }, /* EMA_CS[3] */
+};
+
+const struct pinmux_config emifa_pins_cs4[] = {
+       { pinmux(7), 1, 2 }, /* EMA_CS[4] */
+};
+
+const struct pinmux_config emifa_pins_nand[] = {
+       { pinmux(7), 1, 4 },  /* EMA_WE */
+       { pinmux(7), 1, 5 },  /* EMA_OE */
+       { pinmux(9), 1, 0 },  /* EMA_D[7] */
+       { pinmux(9), 1, 1 },  /* EMA_D[6] */
+       { pinmux(9), 1, 2 },  /* EMA_D[5] */
+       { pinmux(9), 1, 3 },  /* EMA_D[4] */
+       { pinmux(9), 1, 4 },  /* EMA_D[3] */
+       { pinmux(9), 1, 5 },  /* EMA_D[2] */
+       { pinmux(9), 1, 6 },  /* EMA_D[1] */
+       { pinmux(9), 1, 7 },  /* EMA_D[0] */
+       { pinmux(12), 1, 5 }, /* EMA_A[2] */
+       { pinmux(12), 1, 6 }, /* EMA_A[1] */
+};
+
+/* NOR pin muxer settings */
+const struct pinmux_config emifa_pins_nor[] = {
+       { pinmux(5), 1, 6 },  /* EMA_BA[1] */
+       { pinmux(6), 1, 6 },  /* EMA_WAIT[1] */
+       { pinmux(7), 1, 4 },  /* EMA_WE */
+       { pinmux(7), 1, 5 },  /* EMA_OE */
+       { pinmux(8), 1, 0 },  /* EMA_D[15] */
+       { pinmux(8), 1, 1 },  /* EMA_D[14] */
+       { pinmux(8), 1, 2 },  /* EMA_D[13] */
+       { pinmux(8), 1, 3 },  /* EMA_D[12] */
+       { pinmux(8), 1, 4 },  /* EMA_D[11] */
+       { pinmux(8), 1, 5 },  /* EMA_D[10] */
+       { pinmux(8), 1, 6 },  /* EMA_D[9] */
+       { pinmux(8), 1, 7 },  /* EMA_D[8] */
+       { pinmux(9), 1, 0 },  /* EMA_D[7] */
+       { pinmux(9), 1, 1 },  /* EMA_D[6] */
+       { pinmux(9), 1, 2 },  /* EMA_D[5] */
+       { pinmux(9), 1, 3 },  /* EMA_D[4] */
+       { pinmux(9), 1, 4 },  /* EMA_D[3] */
+       { pinmux(9), 1, 5 },  /* EMA_D[2] */
+       { pinmux(9), 1, 6 },  /* EMA_D[1] */
+       { pinmux(9), 1, 7 },  /* EMA_D[0] */
+       { pinmux(10), 1, 1 }, /* EMA_A[22] */
+       { pinmux(10), 1, 2 }, /* EMA_A[21] */
+       { pinmux(10), 1, 3 }, /* EMA_A[20] */
+       { pinmux(10), 1, 4 }, /* EMA_A[19] */
+       { pinmux(10), 1, 5 }, /* EMA_A[18] */
+       { pinmux(10), 1, 6 }, /* EMA_A[17] */
+       { pinmux(10), 1, 7 }, /* EMA_A[16] */
+       { pinmux(11), 1, 0 }, /* EMA_A[15] */
+       { pinmux(11), 1, 1 }, /* EMA_A[14] */
+       { pinmux(11), 1, 2 }, /* EMA_A[13] */
+       { pinmux(11), 1, 3 }, /* EMA_A[12] */
+       { pinmux(11), 1, 4 }, /* EMA_A[11] */
+       { pinmux(11), 1, 5 }, /* EMA_A[10] */
+       { pinmux(11), 1, 6 }, /* EMA_A[9] */
+       { pinmux(11), 1, 7 }, /* EMA_A[8] */
+       { pinmux(12), 1, 0 }, /* EMA_A[7] */
+       { pinmux(12), 1, 1 }, /* EMA_A[6] */
+       { pinmux(12), 1, 2 }, /* EMA_A[5] */
+       { pinmux(12), 1, 3 }, /* EMA_A[4] */
+       { pinmux(12), 1, 4 }, /* EMA_A[3] */
+       { pinmux(12), 1, 5 }, /* EMA_A[2] */
+       { pinmux(12), 1, 6 }, /* EMA_A[1] */
+       { pinmux(12), 1, 7 }, /* EMA_A[0] */
+};
index 3772e64..6e998de 100644 (file)
@@ -45,7 +45,8 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
        clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
 
        clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+       setbits_le32(&dv_pll0_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
 
        /*
         * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -82,7 +83,7 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
        writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
 
        /* Program the PostDiv for PLL1 */
-       writel(0x8000, &dv_pll0_regs->postdiv);
+       writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
 
        /* Post divider setting for PLL1 */
        writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
@@ -126,7 +127,8 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
         * VDB has input on MXI pin
         */
        clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+       setbits_le32(&dv_pll1_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
 
        /*
         * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -151,7 +153,7 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
        writel(pllm, &dv_pll1_regs->pllm);
        writel(prediv, &dv_pll1_regs->prediv);
 
-       writel(0x8000, &dv_pll1_regs->postdiv);
+       writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
 
        /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
        writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
@@ -261,21 +263,23 @@ void dm365_vpss_sync_reset(void)
                VPSS_CLK_CTL_VPSS_CLKMD);
 
        /* LPSC SyncReset DDR Clock Enable */
-       writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
-               PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+       writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
+               ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
+               &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
 
        writel((1 << PdNum), &dv_psc_regs->ptcmd);
 
        while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
                ;
-       while (!((readl(&dv_psc_regs->mdstat[47]) &  PSC_MD_STATE_MSK) ==
-               PSC_SYNCRESET))
+       while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
+               PSC_MD_STATE_MSK) == PSC_SYNCRESET))
                ;
 }
 
 void dm365_por_reset(void)
 {
-       if (readl(&dv_pll0_regs->rstype) & 3)
+       if (readl(&dv_pll0_regs->rstype) &
+               (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
                dm365_vpss_sync_reset();
 }
 
@@ -291,19 +295,20 @@ void dm365_psc_init(void)
 
        for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
                if (lpscgroup == 0) {
-                       lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
-                       lpsc_end   = 28;
+                       /* Enabling LPSC 3 to 28 SCR first */
+                       lpsc_start = DAVINCI_LPSC_VPSSMSTR;
+                       lpsc_end   = DAVINCI_LPSC_TIMER1;
                } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
-                       lpsc_start = 38;
-                       lpsc_end   = 47;
+                       lpsc_start = DAVINCI_LPSC_CFG5;
+                       lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
                } else {
-                       lpsc_start = 50;
-                       lpsc_end   = 51;
+                       lpsc_start = DAVINCI_LPSC_MJCP;
+                       lpsc_end   = DAVINCI_LPSC_HDVICP;
                }
 
                /* NEXT=0x3, Enable LPSC's */
                for (i = lpsc_start; i <= lpsc_end; i++)
-                       setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+                       setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
 
                /*
                 * Program goctl to start transition sequence for LPSCs
@@ -322,7 +327,7 @@ void dm365_psc_init(void)
                /* Wait for MODSTAT = ENABLE from LPSC's */
                for (i = lpsc_start; i <= lpsc_end; i++)
                        while (!((readl(&dv_psc_regs->mdstat[i]) &
-                               PSC_MD_STATE_MSK) == 0x3))
+                               PSC_MD_STATE_MSK) == PSC_ENABLE))
                                ;
        }
 }
@@ -332,7 +337,7 @@ static void dm365_emif_init(void)
        writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
        writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
 
-       setbits_le32(&davinci_emif_regs->nandfcr, 1);
+       setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
 
        writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
 
@@ -361,31 +366,12 @@ int post_log(char *format, ...)
 
 void dm36x_lowlevel_init(ulong bootflag)
 {
-       /*
-        * copied from arch/arm/cpu/arm926ejs/start.S
-        *
-        * flush v4 I/D caches
-        */
-       asm("mov        r0, #0");
-       asm("mcr        p15, 0, r0, c7, c7, 0");        /* flush v3/v4 cache */
-       asm("mcr        p15, 0, r0, c8, c7, 0");        /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       asm("mrc        p15, 0, r0, c1, c0, 0");
-       /* clear bits 13, 9:8 (--V- --RS) */
-       asm("bic        r0, r0, #0x00002300");
-       /* clear bits 7, 2:0 (B--- -CAM) */
-       asm("bic        r0, r0, #0x00000087");
-       /* set bit 2 (A) Align */
-       asm("orr        r0, r0, #0x00000002");
-       /* set bit 12 (I) I-Cache */
-       asm("orr        r0, r0, #0x00001000");
-       asm("mcr        p15, 0, r0, c1, c0, 0");
+       struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
+               (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
+               DAVINCI_UART_CTRL_BASE);
 
        /* Mask all interrupts */
-       writel(0x04, &dv_aintc_regs->intctl);
+       writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
        writel(0x0, &dv_aintc_regs->eabase);
        writel(0x0, &dv_aintc_regs->eint0);
        writel(0x0, &dv_aintc_regs->eint1);
@@ -422,7 +408,10 @@ void dm36x_lowlevel_init(ulong bootflag)
         * Fix Power and Emulation Management Register
         * see sprufh2.pdf page 38 Table 22
         */
-       writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+              &davinci_uart_ctrl_regs->pwremu_mgmt);
+
        puts("ddr init\n");
        dm365_ddr_setup();
 
index c71c685..d435e4b 100644 (file)
@@ -29,6 +29,7 @@
 #include <net.h>
 #include <dp83848.h>
 #include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
index df35e44..68650e5 100644 (file)
@@ -22,6 +22,7 @@
 #include <net.h>
 #include <miiphy.h>
 #include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
index 634eda0..3546e7f 100644 (file)
@@ -36,6 +36,7 @@
 #include <net.h>
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
+#include "../../../../../drivers/net/davinci_emac.h"
 
 int ksz8873_is_phy_connected(int phy_addr)
 {
index 733d413..cce1fe4 100644 (file)
@@ -30,6 +30,7 @@
 #include <miiphy.h>
 #include <lxt971a.h>
 #include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
similarity index 90%
rename from board/davinci/common/misc.c
rename to arch/arm/cpu/arm926ejs/davinci/misc.c
index 5aa7605..5f510b6 100644 (file)
@@ -51,16 +51,16 @@ void dram_init_banksize(void)
 #endif
 
 #ifdef CONFIG_DRIVER_TI_EMAC
-
-/* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
+/*
+ * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
  * Returns 1 if found, 0 otherwise.
  */
 int dvevm_read_mac_address(uint8_t *buf)
 {
 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
        /* Read MAC address. */
-       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
-                    (uint8_t *) &buf[0], 6))
+       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
+               CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
                goto i2cerr;
 
        /* Check that MAC address is valid. */
@@ -70,7 +70,8 @@ int dvevm_read_mac_address(uint8_t *buf)
        return 1; /* Found */
 
 i2cerr:
-       printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
+       printf("Read from EEPROM @ 0x%02x failed\n",
+               CONFIG_SYS_I2C_EEPROM_ADDR);
 err:
 #endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
 
@@ -103,15 +104,16 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 
        eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
        if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
-               /* There is no MAC address in the environment, so we initialize
-                * it from the value in the EEPROM. */
+               /*
+                * There is no MAC address in the environment, so we
+                * initialize it from the value in the EEPROM.
+                */
                debug("### Setting environment from EEPROM MAC address = "
                        "\"%pM\"\n",
                        env_enetaddr);
                eth_setenv_enetaddr("ethaddr", rom_enetaddr);
        }
 }
-
 #endif /* CONFIG_DRIVER_TI_EMAC */
 
 #if defined(CONFIG_SOC_DA8XX)
@@ -122,7 +124,6 @@ void irq_init(void)
         * Mask all IRQs by clearing the global enable and setting
         * the enable clear for all the 90 interrupts.
         */
-
        writel(0, &davinci_aintc_regs->ger);
 
        writel(0, &davinci_aintc_regs->hier);
index 8f38056..75314b9 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * (C) Copyright 2010
similarity index 86%
rename from board/pleb2/Makefile
rename to arch/arm/cpu/arm926ejs/mx28/Makefile
index bc29610..7845310 100644 (file)
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 include $(TOPDIR)/config.mk
 
-LIB    = $(obj)lib$(BOARD).o
+LIB    = $(obj)lib$(SOC).o
 
-COBJS  := pleb2.o flash.o
+COBJS  = clock.o mx28.o iomux.o timer.o
 
-SRCS   := $(COBJS:.o=.c)
+SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
+START  := $(addprefix $(obj),$(START))
+
+all:   $(obj).depend $(LIB)
 
-$(LIB):        $(obj).depend $(OBJS)
+$(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c
new file mode 100644 (file)
index 0000000..f698506
--- /dev/null
@@ -0,0 +1,355 @@
+/*
+ * Freescale i.MX28 clock setup code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+#define        PLL_FREQ_KHZ    480000
+#define        PLL_FREQ_COEF   18
+/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
+#define        XTAL_FREQ_KHZ   24000
+
+#define        PLL_FREQ_MHZ    (PLL_FREQ_KHZ / 1000)
+#define        XTAL_FREQ_MHZ   (XTAL_FREQ_KHZ / 1000)
+
+static uint32_t mx28_get_pclk(void)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+       uint32_t clkctrl, clkseq, clkfrac;
+       uint32_t frac, div;
+
+       clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
+
+       /* No support of fractional divider calculation */
+       if (clkctrl &
+               (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
+               return 0;
+       }
+
+       clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+
+       /* XTAL Path */
+       if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
+               div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
+                       CLKCTRL_CPU_DIV_XTAL_OFFSET;
+               return XTAL_FREQ_MHZ / div;
+       }
+
+       /* REF Path */
+       clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
+       frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+       div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
+       return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mx28_get_hclk(void)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+       uint32_t div;
+       uint32_t clkctrl;
+
+       clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
+
+       /* No support of fractional divider calculation */
+       if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
+               return 0;
+
+       div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
+       return mx28_get_pclk() / div;
+}
+
+static uint32_t mx28_get_emiclk(void)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+       uint32_t frac, div;
+       uint32_t clkctrl, clkseq, clkfrac;
+
+       clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+       clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
+
+       /* XTAL Path */
+       if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
+               div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
+                       CLKCTRL_EMI_DIV_XTAL_OFFSET;
+               return XTAL_FREQ_MHZ / div;
+       }
+
+       clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
+
+       /* REF Path */
+       frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
+               CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+       div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
+       return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mx28_get_gpmiclk(void)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+       uint32_t frac, div;
+       uint32_t clkctrl, clkseq, clkfrac;
+
+       clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+       clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
+
+       /* XTAL Path */
+       if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
+               div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+               return XTAL_FREQ_MHZ / div;
+       }
+
+       clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
+
+       /* REF Path */
+       frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
+               CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+       div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+       return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+/*
+ * Set IO clock frequency, in kHz
+ */
+void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       uint32_t div;
+
+       if (freq == 0)
+               return;
+
+       if (io > MXC_IOCLK1)
+               return;
+
+       div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
+
+       if (div < 18)
+               div = 18;
+
+       if (div > 35)
+               div = 35;
+
+       if (io == MXC_IOCLK0) {
+               writel(CLKCTRL_FRAC0_CLKGATEIO0,
+                       &clkctrl_regs->hw_clkctrl_frac0_set);
+               clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+                               CLKCTRL_FRAC0_IO0FRAC_MASK,
+                               div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
+               writel(CLKCTRL_FRAC0_CLKGATEIO0,
+                       &clkctrl_regs->hw_clkctrl_frac0_clr);
+       } else {
+               writel(CLKCTRL_FRAC0_CLKGATEIO1,
+                       &clkctrl_regs->hw_clkctrl_frac0_set);
+               clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+                               CLKCTRL_FRAC0_IO1FRAC_MASK,
+                               div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
+               writel(CLKCTRL_FRAC0_CLKGATEIO1,
+                       &clkctrl_regs->hw_clkctrl_frac0_clr);
+       }
+}
+
+/*
+ * Get IO clock, returns IO clock in kHz
+ */
+static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       uint32_t tmp, ret;
+
+       if (io > MXC_IOCLK1)
+               return 0;
+
+       tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+
+       if (io == MXC_IOCLK0)
+               ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
+                       CLKCTRL_FRAC0_IO0FRAC_OFFSET;
+       else
+               ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
+                       CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+
+       return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
+}
+
+/*
+ * Configure SSP clock frequency, in kHz
+ */
+void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       uint32_t clk, clkreg;
+
+       if (ssp > MXC_SSPCLK3)
+               return;
+
+       clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+                       (ssp * sizeof(struct mx28_register));
+
+       clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
+       while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
+               ;
+
+       if (xtal)
+               clk = XTAL_FREQ_KHZ;
+       else
+               clk = mx28_get_ioclk(ssp >> 1);
+
+       if (freq > clk)
+               return;
+
+       /* Calculate the divider and cap it if necessary */
+       clk /= freq;
+       if (clk > CLKCTRL_SSP_DIV_MASK)
+               clk = CLKCTRL_SSP_DIV_MASK;
+
+       clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
+       while (readl(clkreg) & CLKCTRL_SSP_BUSY)
+               ;
+
+       if (xtal)
+               writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+                       &clkctrl_regs->hw_clkctrl_clkseq_set);
+       else
+               writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+                       &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+/*
+ * Return SSP frequency, in kHz
+ */
+static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       uint32_t clkreg;
+       uint32_t clk, tmp;
+
+       if (ssp > MXC_SSPCLK3)
+               return 0;
+
+       tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+       if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
+               return XTAL_FREQ_KHZ;
+
+       clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+                       (ssp * sizeof(struct mx28_register));
+
+       tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
+
+       if (tmp == 0)
+               return 0;
+
+       clk = mx28_get_ioclk(ssp >> 1);
+
+       return clk / tmp;
+}
+
+/*
+ * Set SSP/MMC bus frequency, in kHz)
+ */
+void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
+{
+       struct mx28_ssp_regs *ssp_regs;
+       const uint32_t sspclk = mx28_get_sspclk(bus);
+       uint32_t reg;
+       uint32_t divide, rate, tgtclk;
+
+       ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+
+       /*
+        * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+        * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+        * CLOCK_RATE could be any integer from 0 to 255.
+        */
+       for (divide = 2; divide < 254; divide += 2) {
+               rate = sspclk / freq / divide;
+               if (rate <= 256)
+                       break;
+       }
+
+       tgtclk = sspclk / divide / rate;
+       while (tgtclk > freq) {
+               rate++;
+               tgtclk = sspclk / divide / rate;
+       }
+       if (rate > 256)
+               rate = 256;
+
+       /* Always set timeout the maximum */
+       reg = SSP_TIMING_TIMEOUT_MASK |
+               (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
+               ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
+       writel(reg, &ssp_regs->hw_ssp_timing);
+
+       debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
+               bus, tgtclk, freq);
+}
+
+uint32_t mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return mx28_get_pclk() * 1000000;
+       case MXC_GPMI_CLK:
+               return mx28_get_gpmiclk() * 1000000;
+       case MXC_AHB_CLK:
+       case MXC_IPG_CLK:
+               return mx28_get_hclk() * 1000000;
+       case MXC_EMI_CLK:
+               return mx28_get_emiclk();
+       case MXC_IO0_CLK:
+               return mx28_get_ioclk(MXC_IOCLK0);
+       case MXC_IO1_CLK:
+               return mx28_get_ioclk(MXC_IOCLK1);
+       case MXC_SSP0_CLK:
+               return mx28_get_sspclk(MXC_SSPCLK0);
+       case MXC_SSP1_CLK:
+               return mx28_get_sspclk(MXC_SSPCLK1);
+       case MXC_SSP2_CLK:
+               return mx28_get_sspclk(MXC_SSPCLK2);
+       case MXC_SSP3_CLK:
+               return mx28_get_sspclk(MXC_SSPCLK3);
+       }
+
+       return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c
new file mode 100644 (file)
index 0000000..9ea411f
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+
+#if    defined(CONFIG_MX23)
+#define        DRIVE_OFFSET    0x200
+#define        PULL_OFFSET     0x400
+#elif  defined(CONFIG_MX28)
+#define        DRIVE_OFFSET    0x300
+#define        PULL_OFFSET     0x600
+#else
+#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#endif
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad)
+{
+       u32 reg, ofs, bp, bm;
+       void *iomux_base = (void *)MXS_PINCTRL_BASE;
+       struct mx28_register *mxs_reg;
+
+       /* muxsel */
+       ofs = 0x100;
+       ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
+       bp = PAD_PIN(pad) % 16 * 2;
+       bm = 0x3 << bp;
+       reg = readl(iomux_base + ofs);
+       reg &= ~bm;
+       reg |= PAD_MUXSEL(pad) << bp;
+       writel(reg, iomux_base + ofs);
+
+       /* drive */
+       ofs = DRIVE_OFFSET;
+       ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
+       /* mA */
+       if (PAD_MA_VALID(pad)) {
+               bp = PAD_PIN(pad) % 8 * 4;
+               bm = 0x3 << bp;
+               reg = readl(iomux_base + ofs);
+               reg &= ~bm;
+               reg |= PAD_MA(pad) << bp;
+               writel(reg, iomux_base + ofs);
+       }
+       /* vol */
+       if (PAD_VOL_VALID(pad)) {
+               bp = PAD_PIN(pad) % 8 * 4 + 2;
+               mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+               if (PAD_VOL(pad))
+                       writel(1 << bp, &mxs_reg->reg_set);
+               else
+                       writel(1 << bp, &mxs_reg->reg_clr);
+       }
+
+       /* pull */
+       if (PAD_PULL_VALID(pad)) {
+               ofs = PULL_OFFSET;
+               ofs += PAD_BANK(pad) * 0x10;
+               bp = PAD_PIN(pad);
+               mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+               if (PAD_PULL(pad))
+                       writel(1 << bp, &mxs_reg->reg_set);
+               else
+                       writel(1 << bp, &mxs_reg->reg_clr);
+       }
+
+       return 0;
+}
+
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
+{
+       const iomux_cfg_t *p = pad_list;
+       int i;
+       int ret;
+
+       for (i = 0; i < count; i++) {
+               ret = mxs_iomux_setup_pad(*p);
+               if (ret)
+                       return ret;
+               p++;
+       }
+
+       return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
new file mode 100644 (file)
index 0000000..088c019
--- /dev/null
@@ -0,0 +1,221 @@
+/*
+ * Freescale i.MX28 common code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* 1 second delay should be plenty of time for block reset. */
+#define        RESET_MAX_TIMEOUT       1000000
+
+#define        MX28_BLOCK_SFTRST       (1 << 31)
+#define        MX28_BLOCK_CLKGATE      (1 << 30)
+
+/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
+inline void lowlevel_init(void) {}
+
+void reset_cpu(ulong ignored) __attribute__((noreturn));
+
+void reset_cpu(ulong ignored)
+{
+
+       struct mx28_rtc_regs *rtc_regs =
+               (struct mx28_rtc_regs *)MXS_RTC_BASE;
+
+       /* Wait 1 uS before doing the actual watchdog reset */
+       writel(1, &rtc_regs->hw_rtc_watchdog);
+       writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
+
+       /* Endless loop, reset will exit from here */
+       for (;;)
+               ;
+}
+
+int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+{
+       while (--timeout) {
+               if ((readl(&reg->reg) & mask) == mask)
+                       break;
+               udelay(1);
+       }
+
+       return !timeout;
+}
+
+int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+{
+       while (--timeout) {
+               if ((readl(&reg->reg) & mask) == 0)
+                       break;
+               udelay(1);
+       }
+
+       return !timeout;
+}
+
+int mx28_reset_block(struct mx28_register *reg)
+{
+       /* Clear SFTRST */
+       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+
+       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+               return 1;
+
+       /* Clear CLKGATE */
+       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+
+       /* Set SFTRST */
+       writel(MX28_BLOCK_SFTRST, &reg->reg_set);
+
+       /* Wait for CLKGATE being set */
+       if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+               return 1;
+
+       /* Clear SFTRST */
+       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+
+       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+               return 1;
+
+       /* Clear CLKGATE */
+       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+
+       if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+               return 1;
+
+       return 0;
+}
+
+void mx28_fixup_vt(uint32_t start_addr)
+{
+       uint32_t *vt = (uint32_t *)0x20;
+       int i;
+
+       for (i = 0; i < 8; i++)
+               vt[i] = start_addr + (4 * i);
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+       mx28_fixup_vt(gd->relocaddr);
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       extern uint32_t _start;
+
+       mx28_fixup_vt((uint32_t)&_start);
+
+       /*
+        * Enable NAND clock
+        */
+       /* Clear bypass bit */
+       writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
+               &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+       /* Set GPMI clock to ref_gpmi / 12 */
+       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
+               CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
+
+       udelay(1000);
+
+       /*
+        * Configure GPIO unit
+        */
+       mxs_gpio_init();
+
+       return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       printf("Freescale i.MX28 family\n");
+       return 0;
+}
+#endif
+
+int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       printf("CPU:   %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("BUS:   %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
+       printf("EMI:   %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
+       printf("GPMI:  %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
+       return 0;
+}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ */
+#ifdef CONFIG_CMD_NET
+int cpu_eth_init(bd_t *bis)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+       /* Turn on ENET clocks */
+       clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+               CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
+
+       /* Set up ENET PLL for 50 MHz */
+       /* Power on ENET PLL */
+       writel(CLKCTRL_PLL2CTRL0_POWER,
+               &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
+
+       udelay(10);
+
+       /* Gate on ENET PLL */
+       writel(CLKCTRL_PLL2CTRL0_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
+
+       /* Enable pad output */
+       setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
+
+       return 0;
+}
+#endif
+
+U_BOOT_CMD(
+       clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
+       "display clocks",
+       ""
+);
diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mx28/timer.c
new file mode 100644 (file)
index 0000000..dbc904d
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * Freescale i.MX28 timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+/* Maximum fixed count */
+#define TIMER_LOAD_VAL 0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastdec (gd->lastinc)
+
+/*
+ * This driver uses 1kHz clock source.
+ */
+#define        MX28_INCREMENTER_HZ             1000
+
+static inline unsigned long tick_to_time(unsigned long tick)
+{
+       return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+static inline unsigned long time_to_tick(unsigned long time)
+{
+       return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+/* Calculate how many ticks happen in "us" microseconds */
+static inline unsigned long us_to_tick(unsigned long us)
+{
+       return (us * MX28_INCREMENTER_HZ) / 1000000;
+}
+
+int timer_init(void)
+{
+       struct mx28_timrot_regs *timrot_regs =
+               (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+
+       /* Reset Timers and Rotary Encoder module */
+       mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+
+       /* Set fixed_count to 0 */
+       writel(0, &timrot_regs->hw_timrot_fixed_count0);
+
+       /* Set UPDATE bit and 1Khz frequency */
+       writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
+               TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
+               &timrot_regs->hw_timrot_timctrl0);
+
+       /* Set fixed_count to maximal value */
+       writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+
+       return 0;
+}
+
+ulong get_timer(ulong base)
+{
+       struct mx28_timrot_regs *timrot_regs =
+               (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+
+       /* Current tick value */
+       uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
+
+       if (lastdec >= now) {
+               /*
+                * normal mode (non roll)
+                * move stamp forward with absolut diff ticks
+                */
+               timestamp += (lastdec - now);
+       } else {
+               /* we have rollover of decrementer */
+               timestamp += (TIMER_LOAD_VAL - now) + lastdec;
+
+       }
+       lastdec = now;
+
+       return tick_to_time(timestamp) - base;
+}
+
+/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
+#define        MX28_HW_DIGCTL_MICROSECONDS     0x8001c0c0
+
+void __udelay(unsigned long usec)
+{
+       uint32_t old, new, incr;
+       uint32_t counter = 0;
+
+       old = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+       while (counter < usec) {
+               new = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+               /* Check if the timer wrapped. */
+               if (new < old) {
+                       incr = 0xffffffff - old;
+                       incr += new;
+               } else {
+                       incr = new - old;
+               }
+
+               /*
+                * Check if we are close to the maximum time and the counter
+                * would wrap if incremented. If that's the case, break out
+                * from the loop as the requested delay time passed.
+                */
+               if (counter + incr < counter)
+                       break;
+
+               counter += incr;
+               old = new;
+       }
+}
index 0052dab..02332ee 100644 (file)
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <linux/compiler.h>
 
 #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
 
@@ -151,8 +152,8 @@ int print_cpuinfo (void)
        u8 die_rev;
        u32 omap_id;
        u8 cpu_type;
-       u32 system_serial_high;
-       u32 system_serial_low;
+       __maybe_unused u32 system_serial_high;
+       __maybe_unused u32 system_serial_low;
        u32 system_rev = 0;
 
        jtag_id = omap_get_jtag_id();
index 339c5ed..6a09c02 100644 (file)
@@ -194,9 +194,7 @@ reset:
         * we do sys-critical inits only at reboot,
         * not when booting from ram!
         */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_crit
-#endif
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
@@ -301,10 +299,12 @@ clear_bss:
 #endif
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
 #ifndef CONFIG_SPL_BUILD
        bl coloured_LED_init
@@ -353,7 +353,6 @@ _dynsym_start_ofs:
  *
  *************************************************************************
  */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
        /*
         * flush v4 I/D caches
@@ -372,14 +371,15 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
        /*
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
        bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
-       mov     pc, lr          /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+       mov     pc, lr          /* back to my caller */
 
 #ifndef CONFIG_SPL_BUILD
 /*
index 92a5a96..f97fa3d 100644 (file)
@@ -29,10 +29,10 @@ START       := start.o
 
 ifndef CONFIG_SPL_BUILD
 COBJS  += cache_v7.o
-COBJS  += cpu.o
 endif
 
-COBJS  += syslib.o
+COBJS  += cpu.o
+COBJS  += syslib.o
 
 SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
index 091e3e0..662c496 100644 (file)
@@ -65,6 +65,7 @@ int cleanup_before_linux(void)
         * dcache_disable() in turn flushes the d-cache and disables MMU
         */
        dcache_disable();
+       v7_outer_cache_disable();
 
        /*
         * After D-cache is flushed and before it is disabled there may
index 0769a64..933ce05 100644 (file)
@@ -91,7 +91,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
        if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
                refclk *= 2;
 
-       refclk /= pdf + 1;
+       do_div(refclk, pdf + 1);
        temp = refclk * mfn_abs;
        do_div(temp, mfd + 1);
        ret = refclk * mfi;
index 1dee81f..a684611 100644 (file)
@@ -33,6 +33,13 @@ ifdef CONFIG_OMAP
 COBJS  += gpio.o
 endif
 
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+COBJS  += hwinit-common.o
+COBJS  += clocks-common.o
+COBJS  += emif-common.o
+SOBJS  += lowlevel_init.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 COBJS  += spl.o
 ifdef CONFIG_SPL_NAND_SUPPORT
@@ -43,6 +50,12 @@ COBJS        += spl_mmc.o
 endif
 endif
 
+ifndef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+COBJS  += mem-common.o
+endif
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
new file mode 100644 (file)
index 0000000..1da90a4
--- /dev/null
@@ -0,0 +1,599 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *     Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+static inline u32 __get_sys_clk_index(void)
+{
+       u32 ind;
+       /*
+        * For ES1 the ROM code calibration of sys clock is not reliable
+        * due to hw issue. So, use hard-coded value. If this value is not
+        * correct for any board over-ride this function in board file
+        * From ES2.0 onwards you will get this information from
+        * CM_SYS_CLKSEL
+        */
+       if (omap_revision() == OMAP4430_ES1_0)
+               ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+       else {
+               /* SYS_CLKSEL - 1 to match the dpll param array indices */
+               ind = (readl(&prcm->cm_sys_clksel) &
+                       CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+       }
+       return ind;
+}
+
+u32 get_sys_clk_index(void)
+       __attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+       u8 index = get_sys_clk_index();
+       return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+       struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+       clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+                       CM_CLKMODE_DPLL_DPLL_EN_MASK,
+                       DPLL_EN_FAST_RELOCK_BYPASS <<
+                       CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+       struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+       if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+                               LDELAY)) {
+               printf("Bypassing DPLL failed %p\n", base);
+       }
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+       struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+       clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+                     CM_CLKMODE_DPLL_DPLL_EN_MASK,
+                     DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+       struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+       if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+               &dpll_regs->cm_idlest_dpll, LDELAY)) {
+               printf("DPLL locking failed for %p\n", base);
+               hang();
+       }
+}
+
+inline u32 check_for_lock(u32 *const base)
+{
+       struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+       u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
+
+       return lock;
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+                               u8 lock, char *dpll)
+{
+       u32 temp, M, N;
+       struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+       temp = readl(&dpll_regs->cm_clksel_dpll);
+
+       if (check_for_lock(base)) {
+               /*
+                * The Dpll has already been locked by rom code using CH.
+                * Check if M,N are matching with Ideal nominal opp values.
+                * If matches, skip the rest otherwise relock.
+                */
+               M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
+               N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
+               if ((M != (params->m)) || (N != (params->n))) {
+                       debug("\n %s Dpll locked, but not for ideal M = %d,"
+                               "N = %d values, current values are M = %d,"
+                               "N= %d" , dpll, params->m, params->n,
+                               M, N);
+               } else {
+                       /* Dpll locked with ideal values for nominal opps. */
+                       debug("\n %s Dpll already locked with ideal"
+                                               "nominal opp values", dpll);
+                       goto setup_post_dividers;
+               }
+       }
+
+       bypass_dpll(base);
+
+       /* Set M & N */
+       temp &= ~CM_CLKSEL_DPLL_M_MASK;
+       temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+       temp &= ~CM_CLKSEL_DPLL_N_MASK;
+       temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+       writel(temp, &dpll_regs->cm_clksel_dpll);
+
+       /* Lock */
+       if (lock)
+               do_lock_dpll(base);
+
+setup_post_dividers:
+       setup_post_dividers(base, params);
+
+       /* Wait till the DPLL locks */
+       if (lock)
+               wait_for_lock(base);
+}
+
+u32 omap_ddr_clk(void)
+{
+       u32 ddr_clk, sys_clk_khz, omap_rev, divider;
+       const struct dpll_params *core_dpll_params;
+
+       omap_rev = omap_revision();
+       sys_clk_khz = get_sys_clk_freq() / 1000;
+
+       core_dpll_params = get_core_dpll_params();
+
+       debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+       /* Find Core DPLL locked frequency first */
+       ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+                       (core_dpll_params->n + 1);
+
+       if (omap_rev < OMAP5430_ES1_0) {
+               /*
+                * DDR frequency is PHY_ROOT_CLK/2
+                * PHY_ROOT_CLK = Fdpll/2/M2
+                */
+               divider = 4;
+       } else {
+               /*
+                * DDR frequency is PHY_ROOT_CLK
+                * PHY_ROOT_CLK = Fdpll/2/M2
+                */
+               divider = 2;
+       }
+
+       ddr_clk = ddr_clk / divider / core_dpll_params->m2;
+       ddr_clk *= 1000;        /* convert to Hz */
+       debug("ddr_clk %d\n ", ddr_clk);
+
+       return ddr_clk;
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0  : 600 MHz
+ * 4430 ES2.x  : 792 MHz (OPP Turbo)
+ * 4460                : 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+       const struct dpll_params *params;
+       struct dpll_regs *mpu_dpll_regs;
+       u32 omap_rev;
+       omap_rev = omap_revision();
+
+       /*